Abstract: An integrated circuit having a plurality of integrated circuit portions where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry selects a selected voltage of the plurality of voltages and provides an indication of the selected voltage to adjust the supply voltage to the integrated circuit. In one embodiment, the indication may correspond to an analog signal proportional to the selected voltage such as e.g. at the selected voltage or at a voltage less than or greater than the selected voltage. In one embodiment, the selected voltage corresponds to a maximum voltage of the plurality of voltages which may be selected based on sensing the plurality of voltages or based on a plurality of voltage level indicators which set the plurality of voltages. A power supply system, coupled to the integrated circuit, may be used to receive the indication of the selected voltage and adjust the supply voltage based on the indication.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.

Abstract: Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

Abstract: Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.

Abstract: A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.

Abstract: An integrated circuit (10) includes a multiple voltage digital multiplexer circuit (30) for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer (30) includes an analog multiplexer (32) for receiving the digital signals, a level shifter (40) coupled to the output of the analog multiplexer (32), and a supply voltage multiplexer (34) for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit (38, 39) is used to control the input selection of the analog multiplexer (32) as well as the supply voltage multiplexer (34) for providing the correct supply voltage to the level shifter (40). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC (10).

Abstract: A system and method of varying frequency is disclosed. A first oscillator in a phase-locked loop (PLL) maintains a first frequency as part of the PLL lock. A second oscillator having a control coupled to the PLL can be modified to generate a frequency different than that of the PLL. This is accomplished while maintaining lock of the PLL.

Abstract: A system and method of varying frequency is disclosed. A first oscillator in a phase-locked loop (PLL) maintains a first frequency as part of the PLL lock. A second oscillator having a control coupled to the PLL can be modified to generate a frequency different than that of the PLL. This is accomplished while maintaining lock of the PLL.

Abstract: A well bias controller receives input from a sensor. The sensor indicates when a desired threshold condition, such as a temperature or current limit has been exceeded. Threshold conditions are chosen so that when the threshold condition is exceeded, the amount of current drawn by the well bias circuit and through the transistor exceeds the amount of leakage current that would otherwise occur in the device if a well bias circuit were not used. Whenever it is determined, based on the threshold condition, that the well bias circuit is using more current than a device would otherwise leak, the controller turns the well bias circuit off.

Abstract: A well bias controller receives input from a sensor. The sensor indicates when a desired threshold condition, such as a temperature or current limit has been exceeded. Threshold conditions are chosen so that when the threshold condition is exceeded, the amount of current drawn by the well bias circuit and through the transistor exceeds the amount of leakage current that would otherwise occur in the device if a well bias circuit were not used. Whenever it is determined, based on the threshold condition, that the well bias circuit is using more current than a device would otherwise leak, the controller turns the well bias circuit off.