Patents by Inventor Christopher Connor
Christopher Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112100Abstract: An example device includes a user interface component that implements a user interface and receives a visualization request value from user operations; an inspection database comprising an aggregation of inspection data; and a controller, comprising: a facility planning circuit that interprets a user facility visualization value in response to the visualization request value; a facility inspection data circuit that interprets the aggregation of inspection data in response to the user facility visualization value; a geographic depiction circuit that determines a geographic display boundary and a hierarchical inspection presentation for at least one industrial facility positioned within the geographic display boundary in response to the user facility visualization value and the aggregation of inspection data, and determines a user geographic display value in response to the geographic display boundary and the hierarchical inspection presentation.Type: ApplicationFiled: October 2, 2023Publication date: April 4, 2024Inventors: Edward A. Bryner, Richard Ducott, William Barley, Patrick Celentano, Christopher Connor Hazen, Mark Jacob Loosararian, Troy Demmer, Timothy R. Yousaf, Thomas J. Fiorelli
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Publication number: 20230080212Abstract: A thin film transistor (TFT) structure. In an example, the TFT includes a gate electrode, a first layer comprising an oxide semiconductor material, and a second layer between the first layer and the gate electrode. The second layer is crystalline and is in contact with the first layer, and includes zirconium and oxygen. The TFT includes a first contact coupled to the first layer at a first location, and a second contact coupled to the first layer at a second location. In some cases, the second layer further includes hafnium. In some cases, the TFT includes a third layer between of the gate electrode and the second layer, the third layer comprising a metal and oxygen. The gate electrode may also include the metal. In some cases, hydrogen is present at an interface between the gate electrode and the second layer.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Christopher Connor, James O'Donnell, Shailesh Kumar Madisetti
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Patent number: 11264094Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.Type: GrantFiled: March 5, 2018Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Bruce Querbach, Christopher Connor
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Processor having embedded non-volatile random access memory to support processor monitoring software
Patent number: 11074151Abstract: A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.Type: GrantFiled: March 30, 2018Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Bruce Querbach, Christopher Connor -
Patent number: 10878100Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.Type: GrantFiled: October 17, 2018Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Christopher Connor, Bruce Querbach
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Patent number: 10691466Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.Type: GrantFiled: April 2, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Christopher Connor, Bruce Querbach
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Patent number: 10599313Abstract: A system and user interface capable of effectively manipulating high volumes of data is provided. The system and/or user interface is specially-configured to aggregate large data volumes and translate the large data volumes into summary information associated with navigable categorizations (e.g., categorizations linked to selectable visualizations in the user interface) that enable dynamic selection and visualization of portions of the large data volumes. In one particular example, the system and/or user interface is adapted to generate selectable panels having a plurality of build or editing tools displayed coextensive with portions of the large volumes of data. Such panels may be particularly useful for generating a placement (e.g., an advertisement) while reviewing or managing large amounts of information, such as ad placement and performance information for hundreds or thousands or advertisements.Type: GrantFiled: October 11, 2016Date of Patent: March 24, 2020Assignee: Nanigans, Inc.Inventors: Ric Calvillo, Claude Denton, Joshua Allen Breckman, Per Anders Sandell, Derek J. Yimoyines, Amit Deepak Adur, Christopher Connors, Jonathan Palmer
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Publication number: 20190050573Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: Christopher CONNOR, Bruce QUERBACH
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Publication number: 20190043570Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 5, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Bruce Querbach, Christopher Connor
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Publication number: 20190042351Abstract: Examples include techniques for self-healing of a processor in a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores detect an error causing a core failure, update processor configuration information that reflects the core failure, and cause reset and initialization of the processor using the updated processor configuration information.Type: ApplicationFiled: April 2, 2018Publication date: February 7, 2019Inventors: Christopher CONNOR, Bruce QUERBACH
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Publication number: 20190045062Abstract: A call is setup between an originating device (A) and a terminating device (B), which both have access to a public land mobile network (131, 132) and a mobile data network (121, 122). The originating and terminating devices device (A; B) include a respective software-implemented call handling tool (SWA; SWB) configured to assist a user in placing and receiving calls. Bridge nodes (140) are connected to the mobile data network (121, 122), the public land mobile network (131, 132) and a server node (110), which also is connected to the mobile data network (121, 122). In response to a call-setup command from a user of the originating device (A), the software-implemented call handling tool (SWA), on one hand, sends a call-setup request (1) to the server node (110); and on the other hand, makes a first call (2) to a first bridge node (140) over the public land mobile network (131) using a first telephone number (#1).Type: ApplicationFiled: September 27, 2016Publication date: February 7, 2019Applicant: Rebtel Networks ABInventors: Johan Dahlqvist, Vasco Preto, Andrew Kaminski, Thomas Kyritsis, Pär Lindhe, Thomas Skoglund, Suresh Kumar, Amir Mortazavi, Christopher Connor
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Publication number: 20190042275Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.Type: ApplicationFiled: April 2, 2018Publication date: February 7, 2019Inventors: Christopher CONNOR, Bruce QUERBACH
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PROCESSOR HAVING EMBEDDED NON-VOLATILE RANDOM ACCESS MEMORY TO SUPPORT PROCESSOR MONITORING SOFTWARE
Publication number: 20190042383Abstract: A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Inventors: Bruce QUERBACH, Christopher CONNOR -
Publication number: 20180324305Abstract: A group call is setup between one originating device (A) and at least two terminating devices (B, C), which each has access to a public land mobile network (131, 132, 133) and a mobile data net-work (121, 122, 123). The originating and terminating devices (A, B, C) include a respective software-implemented call handling tool (SWA, SWB, SWC) configured to assist a user in placing and receiving group calls. Bridge nodes (141, 142, 143) are connected to the mobile data network (121, 122, 123), the public land mobile network (131, 132, 133) and a server node (110), which, in turn, also is connected to the mobile data network (121, 122, 123).Type: ApplicationFiled: October 10, 2016Publication date: November 8, 2018Inventors: Johan Dahlqvist, Vasco Preto, Andrew Kaminski, Thomas Kyritsis, Pär Lindhe, Thomas Skoglund, Suresh Kumar, Amir Mortazavi, Christopher Connor
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Publication number: 20170262165Abstract: A system and user interface capable of effectively manipulating high volumes of data is provided. The system and/or user interface is specially-configured to aggregate large data volumes and translate the large data volumes into summary information associated with navigable categorizations (e.g., categorizations linked to selectable visualizations in the user interface) that enable dynamic selection and visualization of portions of the large data volumes. In one particular example, the system and/or user interface is adapted to generate selectable panels having a plurality of build or editing tools displayed coextensive with portions of the large volumes of data. Such panels may be particularly useful for generating a placement (e.g., an advertisement) while reviewing or managing large amounts of information, such as ad placement and performance information for hundreds or thousands or advertisements.Type: ApplicationFiled: October 11, 2016Publication date: September 14, 2017Applicant: Nanigans, Inc.Inventors: Ric Calvillo, Claude Denton, Joshua Allen Breckman, Per Anders Sandell, Derek J. Yimoyines, Amit Deepak Adur, Christopher Connors, Jonathan Palmer
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Publication number: 20170102866Abstract: A system and user interface capable of effectively manipulating high volumes of data is provided. The system and/or user interface is specially-configured to aggregate large data volumes and translate the large data volumes into summary information associated with navigable categorizations (e.g., categorizations linked to selectable visualizations in the user interface) that enable dynamic selection and visualization of portions of the large data volumes. In one particular example, the system and/or user interface is adapted to generate selectable panels having a plurality of build or editing tools displayed coextensive with portions of the large volumes of data. Such panels may be particularly useful for generating a placement (e.g., an advertisement) while reviewing or managing large amounts of information, such as ad placement and performance information for hundreds or thousands or advertisements.Type: ApplicationFiled: October 11, 2016Publication date: April 13, 2017Applicant: Nanigans, Inc.Inventors: Ric Calvillo, Claude Denton, Joshua Allen Breckman, Per Anders Sandell, Derek A. Yimoyines, Amit Deepak Adur, Christopher Connors, Jonathan Palmer
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Publication number: 20160364770Abstract: A system and user interface capable of effectively manipulating high volumes of data is provided. The system and/or user interface is specially-configured to aggregate large data volumes and translate the large data volumes into summary information associated with navigable categorizations (e.g., categorizations linked to selectable visualizations in the user interface) that enable dynamic selection and visualization of portions of the large data volumes. In one particular example, the system and/or user interface is adapted to generate selectable panels having a plurality of build or editing tools displayed coextensive with portions of the large volumes of data. Such panels may be particularly useful for generating a placement (e.g., an advertisement) while reviewing or managing large amounts of information, such as ad placement and performance information for hundreds or thousands or advertisements.Type: ApplicationFiled: May 27, 2016Publication date: December 15, 2016Applicant: Nanigans, Inc.Inventors: Claude Denton, Ric Calvillo, Joshua Allen Breckman, Per Anders Sandell, Derek J. Yimoyines, Amit Deepak Adur, Christopher Connors, Jonathan Palmer
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Publication number: 20100023358Abstract: A machine-implemented method for analyzing risk associated with an activity may include receiving inputs identifying a user and an activity to be analyzed, selecting a boundary dataset including operator data, vehicle/equipment data, and/or general operations data, selecting a boundary parameter from the selected dataset, selecting an environmental parameter associated with the selected boundary parameter, and determining whether the selected environmental parameter exceeds a threshold level of risk associated with the selected boundary parameter.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: Polaris Aero, LLCInventors: James T. Fox, Christopher A. Connor
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Publication number: 20060188620Abstract: System for making and delivering a customized beverage product to a consumer having a user interface, a customization director in communication with a customization data store and the user interface, wherein the customization director includes executable instructions for determining a users customized formulation; and a beverage delivery system in communication with the customization director, wherein the beverage delivery system includes executable instructions for delivering a customized beverage product. Method for delivering a customized beverage product to an individual including the steps of obtaining consumer preference data; determining a consumer beverage formulation corresponding to the consumer preference data; and providing the consumer a customized beverage corresponding to the customized beverage formulation, utilizing one or more of delayed dilution, delayed mixing, and delayed filtering, in any order.Type: ApplicationFiled: March 22, 2006Publication date: August 24, 2006Inventors: Roger Gutwein, Christopher Connor
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Patent number: D796843Type: GrantFiled: April 1, 2016Date of Patent: September 12, 2017Inventor: Christopher Connor