Patents by Inventor Christopher D. Bryant
Christopher D. Bryant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240427728Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: ApplicationFiled: May 21, 2024Publication date: December 26, 2024Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Patent number: 12007938Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: GrantFiled: May 30, 2022Date of Patent: June 11, 2024Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Publication number: 20240054077Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Inventor: Christopher D. Bryant
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Patent number: 11822486Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.Type: GrantFiled: June 27, 2020Date of Patent: November 21, 2023Assignee: Intel CorporationInventor: Christopher D. Bryant
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Publication number: 20230195634Abstract: An embodiment of an integrated circuit may comprise a prefetcher, a model specific register that is accessible at runtime to store information associated with the prefetcher, and circuitry communicatively coupled to the model specific register and prefetcher to adjust a runtime operation of the prefetcher based on the information associated with the prefetcher stored in the model specific register. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Krishna Ganapathy, Kameswar Subramaniam, Christopher D Bryant, Taylor Morrow
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Publication number: 20220405234Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: ApplicationFiled: May 30, 2022Publication date: December 22, 2022Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Patent number: 11347680Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: GrantFiled: December 22, 2020Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Publication number: 20210406194Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.Type: ApplicationFiled: June 27, 2020Publication date: December 30, 2021Inventor: Christopher D. Bryant
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Publication number: 20210117372Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: ApplicationFiled: December 22, 2020Publication date: April 22, 2021Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Patent number: 10901940Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: GrantFiled: April 2, 2016Date of Patent: January 26, 2021Assignee: INTEL CORPORATIONInventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Patent number: 10067762Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.Type: GrantFiled: July 1, 2016Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Vikash Agarwal, Christopher D. Bryant, Jonathan D. Combs, Stephen J. Robinson
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Patent number: 9921968Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.Type: GrantFiled: December 31, 2016Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Christopher D. Bryant, Rama S. Gopal
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Patent number: 9921967Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.Type: GrantFiled: July 26, 2011Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Christopher D. Bryant, Rama S. Gopal
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Patent number: 9892059Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.Type: GrantFiled: December 31, 2016Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Christopher D. Bryant, Rama S. Gopal
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Patent number: 9892056Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.Type: GrantFiled: December 31, 2016Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Christopher D. Bryant, Rama S. Gopal
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Patent number: 9875187Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.Type: GrantFiled: December 10, 2014Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Christopher D. Bryant, Stephen J. Robinson
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Publication number: 20170286113Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.Type: ApplicationFiled: April 2, 2016Publication date: October 5, 2017Applicant: INTEL CORPORATIONInventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
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Patent number: 8769539Abstract: A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the apparatus. One embodiment of the method includes determining whether a first group, comprising at least one or more instructions, is to be selected from a scheduling queue of a processor for execution using either a first execution mode or a second execution mode. The method also includes, responsive to determining that the first group is to be selected for execution using the second execution mode, preventing selection of the first group until a second group, comprising at least one or more instructions, that entered the scheduling queue prior to the first group is selected for execution.Type: GrantFiled: November 16, 2010Date of Patent: July 1, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Daniel Hopper, Suzanne Plummer, Christopher D. Bryant
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Patent number: 8713263Abstract: The present invention provides a method and apparatus for supporting embodiments of an out-of-order load/store queue structure. One embodiment of the apparatus includes a first queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes one or more additional queues for storing memory operation in response to completion of a memory operation. The embodiment of the apparatus is configured to remove the memory operation from the first queue in response to the completion.Type: GrantFiled: November 1, 2010Date of Patent: April 29, 2014Assignee: Advanced Micro Devices, Inc.Inventor: Christopher D. Bryant
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Patent number: 8645588Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.Type: GrantFiled: November 1, 2010Date of Patent: February 4, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Christopher D. Bryant, David Kaplan