Patents by Inventor Christopher D. Ebeling
Christopher D. Ebeling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146711Abstract: A unified platform may comprise a combination of independent frameworks that have been integrated and configured to collaboratively operate seamlessly. In some aspects, the unified platform may comprise one or more of an authentication and authorization framework, a dynamic user interface framework, a workflow state management framework, a notification and active data loss and prevention (DLP) engine framework, and an orchestration engine framework. Each of the frameworks included in the unified platform may comprise one or more of the plurality of computing devices executing computer-readable program instructions.Type: ApplicationFiled: October 5, 2023Publication date: May 2, 2024Applicant: Citizens Financial Group, Inc.Inventors: Rajesh K. Shah, Arif Sufi, Balamurugan Muthu, Sudip Mukhopadhyay, Deepak Nayak, Senthil K. Ponnappan, Chris Benz, Christopher D. Elomaa, Christine Roberts, Ryan Pearson, Jeffrey M. Mayerson, Christopher C. Ebeling
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Publication number: 20240146708Abstract: A unified platform may comprise a combination of independent frameworks that have been integrated and configured to collaboratively operate seamlessly. In some aspects, the unified platform may comprise one or more of an authentication and authorization framework, a dynamic user interface framework, a workflow state management framework, a notification and active data loss and prevention (DLP) engine framework, and an orchestration engine framework. Each of the frameworks included in the unified platform may comprise one or more of the plurality of computing devices executing computer-readable program instructions.Type: ApplicationFiled: September 20, 2023Publication date: May 2, 2024Applicant: Citizens Financial Group, Inc.Inventors: Rajesh K. Shah, Arif Sufi, Balamurugan Muthu, Sudip Mukhopadhyay, Deepak Nayak, Michael S. Ruttledge, Dhiraj Rattan, James W. Mitcheson, Nageshwara Rao Chirravuri, Krishna Mopati, Williard D. Stackpole, Kyle R. Berglund, Matthew Eble Darlage, Chris Benz, Christopher D. Elomaa, Brendan Coughlin, Eric Schuppenhauer, Christine Roberts, Ryan Pearson, Jeffrey M. Mayerson, Christopher C. Ebeling
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Patent number: 10354706Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.Type: GrantFiled: November 23, 2015Date of Patent: July 16, 2019Assignee: Altera CorporationInventors: Christopher D. Ebeling, Trevis Chandler
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Publication number: 20180287616Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
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Patent number: 10014865Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.Type: GrantFiled: February 20, 2015Date of Patent: July 3, 2018Assignee: Altera CorporationInventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
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Patent number: 9954530Abstract: An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.Type: GrantFiled: January 19, 2015Date of Patent: April 24, 2018Assignee: Altera CorporationInventors: Christopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
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Patent number: 9639416Abstract: A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are “in-flight” within the feedback loop to the final CRC checksum.Type: GrantFiled: March 14, 2013Date of Patent: May 2, 2017Assignee: Altera CorporationInventors: David Bruce Parlour, Christopher D. Ebeling, Michael Glenn Wrighton, Michael Alan Baxter
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Patent number: 9257986Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: January 28, 2014Date of Patent: February 9, 2016Assignee: Altera CorporationInventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 9203397Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.Type: GrantFiled: December 15, 2012Date of Patent: December 1, 2015Assignee: Altera CorporationInventors: Christopher D. Ebeling, Trevis Chandler
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Patent number: 9148151Abstract: A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.Type: GrantFiled: July 13, 2012Date of Patent: September 29, 2015Assignee: Altera CorporationInventors: Steven Teig, Christopher D. Ebeling, Martin Voogel, Andrew Caldwell
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Publication number: 20150236700Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.Type: ApplicationFiled: February 20, 2015Publication date: August 20, 2015Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
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Publication number: 20150200671Abstract: An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.Type: ApplicationFiled: January 19, 2015Publication date: July 16, 2015Inventors: Christopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
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Patent number: 9000801Abstract: An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.Type: GrantFiled: March 13, 2013Date of Patent: April 7, 2015Assignee: Tabula, Inc.Inventors: Christopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
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Patent number: 8996906Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.Type: GrantFiled: December 3, 2010Date of Patent: March 31, 2015Assignee: Tabula, Inc.Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
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Publication number: 20140210512Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8788987Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: April 6, 2011Date of Patent: July 22, 2014Assignee: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8650514Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: March 21, 2012Date of Patent: February 11, 2014Assignee: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Publication number: 20130097575Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: ApplicationFiled: April 6, 2011Publication date: April 18, 2013Applicant: TABULA, INC.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Publication number: 20130093462Abstract: A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.Type: ApplicationFiled: July 13, 2012Publication date: April 18, 2013Inventors: Steven Teig, Christopher D. Ebeling, Martin Voogel, Andrew Caldwell
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Patent number: 8225187Abstract: A cyclic redundancy check (CRC) bit-slice circuit including a plurality of AND gates coupled with configuration data is described. The configuration data may enable the plurality of AND gates to provide a set of CRC input data and feedback polynomial data meeting a plurality of CRC protocols. The CRC bit-slice circuit accepts a generator polynomial as an input design parameter to build a CRC module. The modularity of the design then allows a larger CRC design to be constructed from multiple CRC modules such that wider data width may be accommodated. Several CRC modules can be cascaded to accommodate various data widths and to meet a plurality of CRC protocols.Type: GrantFiled: March 31, 2008Date of Patent: July 17, 2012Assignee: Xilinx, Inc.Inventors: David P. Schultz, Christopher D. Ebeling