Abstract: Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage.

Abstract: Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage.

Abstract: Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage.

Abstract: In an exemplary embodiment, a spurline filter comprises a capacitive element connected to a spur and either a through-line of the spurline filter or ground. In another embodiment, multiple capacitive elements are connected to the spur. In an exemplary embodiment, the capacitively loaded spurline filter provides a band rejection frequency response similar to the band rejection frequency response of a similar spurline filter that does not comprise at least one capacitive element but the capacitively loaded spurline filter has half the layout area or less. In an exemplary embodiment, the spurline filter comprises capacitive elements, where the capacitive elements are configured to reduce the resonant frequency of the filter.

Abstract: Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: In accordance with an exemplary embodiment of the present invention, a Doherty amplifier is provided for applications in radio frequency, microwave, and other electronic systems. An exemplary Doherty amplifier comprises a first MMIC having a first power detector, and a second MMIC having a second power detector. The first MMIC and the second MMIC are structurally identical. Furthermore, the first MMIC is configured as a carrier amplifier and the second MMIC is configured as a peaking amplifier. In the exemplary embodiment, an amplifier control bias of the carrier amplifier is a function of the power detected by the first power detector and an amplifier control bias of the peaking amplifier is a function of the power detected by the second power detector. The ability to assemble a Doherty amplifier using a single MMIC product results in a simple and less expensive manufacturing process.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: A system and method for high frequency, high power operation communication systems is provided. More particularly, a system and method for a single system-on-chip system monolithic microwave integrated circuit that provides both high-frequency performance at a low cost is provided.

Abstract: In accordance with an exemplary embodiment of the present invention, a Doherty amplifier is provided for applications in radio frequency, microwave, and other electronic systems. An exemplary Doherty amplifier comprises a first MMIC having a first power detector, and a second MMIC having a second power detector. The first MMIC and the second MMIC are structurally identical. Furthermore, the first MMIC is configured as a carrier amplifier and the second MMIC is configured as a peaking amplifier. In the exemplary embodiment, an amplifier control bias of the carrier amplifier is a function of the power detected by the first power detector and an amplifier control bias of the peaking amplifier is a function of the power detected by the second power detector. The ability to assemble a Doherty amplifier using a single MMIC product results in a simple and less expensive manufacturing process.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: In an exemplary embodiment, a spurline filter comprises a capacitive element connected to a spur and either a through-line of the spurline filter or ground. In another embodiment, multiple capacitive elements are connected to the spur. In an exemplary embodiment, the capacitively loaded spurline filter provides a band rejection frequency response similar to the band rejection frequency response of a similar spurline filter that does not comprise at least one capacitive element but the capacitively loaded spurline filter has half the layout area or less. In an exemplary embodiment, the spurline filter comprises capacitive elements, where the capacitive elements are configured to reduce the resonant frequency of the filter.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: A MMIC power amplifier having a smaller die size and higher power output are realized with the improved amplifier and transistor geometry herein provided. In particular, transistors, such as FETs (field effect transistors) are displaced from a conventional FET geometry with alternating FETs being rotated in opposite directions. The inputs (gate pads) and outputs (drain pads) of two adjacent FETs may be “shared.” In a shared input configuration, a compensation network may be coupled to the input. The improved FET configuration reduces the number of splitting and combining networks by up to 50% over the prior art and the die area for a typical 4 watt power amplifier is reduced by 48-72% over the prior art. The improved amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be “folded.

Abstract: A MMIC power amplifier having a smaller die size and higher power output are realized with the improved amplifier and transistor geometry herein provided. In particular, transistors, such as FETs (field effect transistors) are displaced from a conventional FET geometry with alternating FETs being rotated in opposite directions. The inputs (gate pads) and outputs (drain pads) of two adjacent FETs may be “shared.” In a shared input configuration, a compensation network may be coupled to the input. The improved FET configuration reduces the number of splitting and combining networks by up to 50% over the prior art and the die area for a typical 4 watt power amplifier is reduced by 48-72% over the prior art. The improved amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be “folded.

Abstract: A wide bandwidth frequency multiplier (48) multiplies a first frequency of an input signal (52) to generate an output signal (54) having a second frequency. The multiplier (48) includes first stage doubler (56). The doubler (56) includes a lumped element power splitter (62), a push-push amplifier (80), and a combining junction (96). The power splitter (62) splits the input signal (52) into first and second signals (70, 72) that are balanced in phase. A series resistive element (86) maintains amplitude balance between the first and second signals (70, 72). First and second feedback circuits (166, 184) are integrated with first and second transistors (164, 182) so that the push-push amplifier (80) operates over wide bandwidth. In addition, the multiplier (48) includes a second stage doubler (58) configured similar to the first stage doubler (56) for producing an output signal (54) that is quadruple the frequency of input signal (52).