Patents by Inventor Christopher D. Hull

Christopher D. Hull has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923809
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. An output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull
  • Publication number: 20240021522
    Abstract: Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.
    Type: Application
    Filed: December 23, 2020
    Publication date: January 18, 2024
    Inventors: Tolga ACIKALIN, Tae Young YANG, Debabani CHOUDHURY, Shuhei YAMADA, Roya DOOSTNEJAD, Hosein NIKOPOUR, Issy KIPNIS, Oner ORHAN, Mehnaz RAHMAN, Kenneth P. FOUST, Christopher D. HULL, Telesphor KAMGAING, Omkar KARHADE, Stefano PELLERANO, Peter SAGAZIO, Sai VADLAMANI
  • Publication number: 20220399857
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. An output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 15, 2022
    Inventors: Jong Seok PARK, Yanjie WANG, Stefano PELLERANO, Christopher D. HULL
  • Patent number: 11424722
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 23, 2022
    Assignee: INTEL CORPORATION
    Inventors: Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull
  • Publication number: 20220200642
    Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Abhishek AGRAWAL, Ritesh A. BHAT, Steven CALLENDER, Brent R. CARLTON, Christopher D. HULL, Stefano PELLERANO, Mustafijur RAHMAN, Peter SAGAZIO, Woorim SHIN
  • Publication number: 20220200750
    Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Inventors: Peter SAGAZIO, Chun C. LEE, Stefano PELLERANO, Christopher D. HULL
  • Publication number: 20210126589
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Application
    Filed: August 24, 2020
    Publication date: April 29, 2021
    Inventors: Jong Seok PARK, Yanjie WANG, Stefano PELLERANO, Christopher D. HULL
  • Patent number: 10778154
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Publication number: 20200021251
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 16, 2020
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Patent number: 10381986
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Publication number: 20180278216
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Application
    Filed: January 23, 2018
    Publication date: September 27, 2018
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Patent number: 9887673
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. The output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Publication number: 20170264250
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Patent number: 6429502
    Abstract: A novel trench isolated guard ring region for providing RF isolation is disclosed. The semiconductor integrated circuit (IC) device of the present invention comprises a substrate, an insulating layer formed on the substrate, a buried layer formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A first isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer. A second isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A plurality of isolation chambers is formed within the first and second isolation trenches. A collector is implanted into the epitaxial layer in the guard ring region.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: August 6, 2002
    Assignee: Silicon Wave, Inc.
    Inventors: Michael Librizzi, Christopher D. Hull
  • Patent number: 6310387
    Abstract: An integrated circuit inductor structure that includes a shielding pattern that induces a plurality of small eddy currents to shield the magnetic energy generated by the inductor from the substrate of the IC. The IC inductor structure is formed on a Silicon on Insulator (SOI) substrate where the substrate of the SOI has high resistivity. The shielding pattern forms a checkerboard pattern that includes a plurality of conducting regions completely isolated from each other by oxide material. The inductor has a high quality factor and a high self-resonance frequency due to the effective shielding of electromagnetic energy from the substrate of the IC while not reducing the effective inductance of the inductor.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: October 30, 2001
    Assignee: Silicon Wave, Inc.
    Inventors: James Douglas Seefeldt, Christopher D. Hull
  • Patent number: 6172378
    Abstract: Integrated circuit varactor structures that include either an P-gate/N-well or N-gate/P-well layer configuration formed on an SOI substrate. The varactor structure is completely electrically isolated from the substrate of the IC by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structures. The isolation trenches preferably extend to the oxide layer of the SOI substrate. The P-gate/N-well varactor structure includes N+ implant regions formed in an N-well implant layer of the varactor. The N+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the N-well layer where the P-gate is formed over the LOCOS layer. The P-gate may be formed of polysilicon. The N-gate/P-well varactor structure includes P+ implant regions formed in a P-well implant layer of the varactor. The P+ implant regions comprise the source and the drain of a varactor.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: January 9, 2001
    Assignee: Silicon Wave, Inc.
    Inventors: Christopher D. Hull, James Douglas Seefeldt, Kishore V. Seendripu