Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is formed on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with the hollow core.

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

Abstract: A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract: Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.

Abstract: Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.

Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

Abstract: A semiconductor structure with an interconnect level above a substrate and including a conductive pad and a metallic structure, such as a base of a crackstop. A first dielectric layer is above the conductive pad and above the metallic structure. A first opening in the first dielectric layer is aligned with and exposes the conductive pad and a second opening is aligned with and exposes the metallic structure. A metallic liner lines the first opening and the second opening and is on the top surface of the first dielectric layer. A second dielectric layer is above the metallic liner and a third dielectric layer is above the second dielectric layer. A third opening exposes a portion of the metal liner above the conductive pad and a copper plug and pedestal are in the third opening on the exposed portion of the metal liner.

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.