Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j?1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.