Abstract: An integrated delay discriminator for use with a field-programmable gate array including a reference path and a response path. The reference path is associated with a first delay of a first portion of the field-programmable gate array, and is configured to provide an event initiation marker for opening a delay measurement window. The response path is coupled to the reference path and is associated with a second delay of a second portion of the field-programmable gate array. The response path is configured to provide an event termination marker for closing the delay measurement window that was opened by the reference path. This allows a time delay determination measurement between the first portion and the second portion of the field-programmable gate array.

Abstract: A technique for providing high current carrying metal conductors for coupling to transistors or the like to increase the current carrying capacity of the transistor without substantial increase in size. The conductors are tapered along the axis of current flow with current being conducted to or from the tapered portion of the conductors, such that the current density therein is substantially constant.