Patents by Inventor Christopher D. Thomas

Christopher D. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769686
    Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Harinath Reddy, Harsono S. Simka, Christopher D. Thomas
  • Publication number: 20210375662
    Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.
    Type: Application
    Filed: September 29, 2016
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Harinath Reddy, Harsono S. Simka, Christopher D. Thomas
  • Publication number: 20110147851
    Abstract: A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A width of the gate trench comprises between about 8 nm and about 65 nm. The gate comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. In another exemplary embodiment, the gate further comprises a second material formed void free on an interior surface of the first material and comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Christopher D. Thomas, Joseph M. Steigerwald, Timothy E. Glassman, Kyoung H. Kim, Dan S. Lavric, Michael Ollinger, M. N. Perez-Paz
  • Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Publication number: 20080124857
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 29, 2008
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Patent number: 7320935
    Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Jihperng Leu, Christopher D. Thomas
  • Patent number: 7220635
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Chris E. Barns, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Patent number: 7153734
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Patent number: 7001641
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Patent number: 6977224
    Abstract: A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Patent number: 6843852
    Abstract: An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: January 18, 2005
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Vincent R. Caillouette, Christopher D. Thomas, Chin-Chang Cheng
  • Publication number: 20040245107
    Abstract: Embodiments of the invention provide methods of reducing electroplating defects by adjusting immersion conditions. For one embodiment, the immersion conditions are adjusted based upon characteristics of the substrate, including feature size. Additionally or alternatively, the immersion conditions may be adjusted based upon aspects of the electroplating process, including motion of the substrate upon immersion. Immersion conditions that may be adjusted in accordance with various embodiments of the invention include entry bias voltage/current, vertical immersion speed, and angle of immersion.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Guangli Che, Vinay B. Chikarmane, Christopher D. Thomas, Robert I. Wu, Daniel J. Zierath
  • Patent number: 6733679
    Abstract: A method of treating an electroless plating waste is provided. The waste is contained and an ability of a reducing agent to reduce a metal of the waste is decreased, for example by adding a stabilizing chemical or by exposing the waste to an anode to which a positive voltage is applied. Poisonous and explosive gases evolve from the waste, which are vented. Upon completion, the waste is drained.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Christopher D. Thomas
  • Publication number: 20040058139
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Application
    Filed: September 23, 2002
    Publication date: March 25, 2004
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Patent number: 6696758
    Abstract: An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: February 24, 2004
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Publication number: 20040026786
    Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 12, 2004
    Applicant: Intel Corporation
    Inventors: Jihperng Leu, Christopher D. Thomas
  • Patent number: 6605874
    Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Jihperng Leu, Christopher D. Thomas
  • Publication number: 20030134047
    Abstract: An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Inventors: Valery M. Dubin, Vincent R. Caillouette, Christopher D. Thomas, Chin-Chang Cheng
  • Publication number: 20030111729
    Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Applicant: Intel Corporation
    Inventors: Jihperng Leu, Christopher D. Thomas