Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a plurality of second signals by a voltage translation of a plurality of first signals. The second circuit may be configured to switch the second signals to generate a plurality of third signals. The second signals are generally switched such that (i) all third signals are inactive before one of the third signals transitions from inactive to active while a switching condition is enabled and (ii) all third signals are switched inactive while the switching condition is disabled. The third circuit may be configured to amplify the third signals to generate a plurality of output signals. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.

Abstract: An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.

Abstract: An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.

Abstract: An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.

Abstract: An integrated circuit includes a transmit/receive (T/R) circuit and a gate/drain bias control circuit. The transmit/receive (T/R) circuit may be configured to transmit and receive radio frequency (RF) signals. The gate/drain bias control circuit may be configured to enable or disable internal gate switching of one or more amplifiers of the transmit/receive (T/R) circuit in response to a first control signal. When the internal gate switching is disabled the one or more amplifiers of the transmit/receive (T/R) circuit are enabled and disabled solely by external drain switching.

Abstract: A method for single signal transmit/receive module amplifier switching control is disclosed. Step (A) of the method may receive a control signal through a single pin of a circuit. The control signal may alternately conveys (i) a receive mode and (ii) a transmit mode. Step (B) may generate a transmit signal in a disabled state in response to the control signal transitioning from the transmit mode to the receive mode. The transmit signal in the disabled state is generally configured to disable a transmit amplifier. Step (C) may generate a receive signal in an enabled state a receive delay time after the control signal transitions from the transmit mode to the receive mode. The receive signal in the enabled state is generally configured to enable a receive amplifier. The receive delay time may allow the transmit amplifier to switch off before the receive amplifier switches on.

Abstract: An integrated circuit includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal, where the plurality of inputs is received as a serial data stream. The second circuit may be configured to generate one or more pairs of complementary output signals and a plurality of open-drain outputs in response to a third control signal, a fourth control signal, a fifth control signal, and a sixth control signal. A first complementary output of each pair of complementary output signals has a higher current capability than a second complementary output of each pair of complementary output signals.

Abstract: An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.

Abstract: An integrated circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal. The plurality of inputs may be received in parallel in a first mode and as a serial bit stream in a second mode. The second circuit may be configured to generate a plurality of outputs in response to a third control signal and a fourth control signal.

Abstract: An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.

Abstract: A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Abstract: A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Abstract: A high power shunt switch comprises a leadframe including a paddle for supporting a shunt element, and a plurality of bond pads located around a periphery of the paddle, wherein at least a first subset of the bond pads are aligned in a substantially straight-line configuration. A shunt element is fixedly attached to the paddle and wire bonded to a top surface of one the bond pads. An encapsulant is disposed on the paddle, the shunt element, the plurality of bond pads, and the wire bond, thereby forming an encapsulated package structure. The package structure is positioned and attached to a transmission line such that the bottom surfaces of each of the at least first subset of bond pads are in simultaneous contact with the transmission line. The package structure and the transmission line are fixedly attached to a suitable substrate.

Abstract: A high power shunt switch comprises a leadframe including a paddle for supporting a shunt element, and a plurality of bond pads located around a periphery of the paddle, wherein at least a first subset of the bond pads are aligned in a substantially straight-line configuration. A shunt element is fixedly attached to the paddle and wire bonded to a top surface of one the bond pads. An encapsulant is disposed on the paddle, the shunt element, the plurality of bond pads, and the wire bond, thereby forming an encapsulated package structure. The package structure is positioned and attached to a transmission line such that the bottom surfaces of each of the at least first subset of bond pads are in simultaneous contact with the transmission line. The package structure and the transmission line are fixedly attached to a suitable substrate.

Abstract: A multiple-bit digital attenuator with improved frequency response and reduced insertion loss characteristics is provided. The multiple-bit digital attenuator comprises at least one 2-bit digital attenuator. The 2-bit digital attenuator includes a single series switching transistor located between a first terminal and a second terminal and controllable by a reference control signal, a temperature compensation circuit placed in parallel with the series switching transistor and including two temperature compensation transistors, a pair of first shunt circuits located at the first and second terminals and controllable by a first bit control signal, and a second shunt circuit located between the two temperature compensation transistors and controllable by a second bit control signal.