Abstract: An asynchronous circuit that implements a dual pipeline stage is disclosed. The input stage of the circuit receives asynchronous data. A first converter separates the data from the input stage into alternating pipelines to allow parallel execution. A second converter then merges the data from the dual pipelines back into a single output stage. This technique is useful in improving the speed of a circuit, as it allows parallel execution. In other embodiments, the dual pipelines offer fault tolerance. In some embodiments, the protocol used in the input and output stages is different from that employed in the dual pipelines.