Patents by Inventor Christopher David Sonnek

Christopher David Sonnek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adjusting access times to memory cells based on characterized word-line delay and gate delay
    Patent number: 8787099
    Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 22, 2014
    Assignee: LSI Corporation
    Inventors: Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Richard John Stephani, Christopher David Sonnek
  • ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY
    Publication number: 20130343139
    Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: LSI Corporation
    Inventors: Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Richard John Stephani, Christopher David Sonnek