Patents by Inventor Christopher Dolan
Christopher Dolan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9830285Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9830284Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: July 27, 2015Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9824038Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9824037Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160070664Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: October 14, 2015Publication date: March 10, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160071558Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: October 14, 2015Publication date: March 10, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160034420Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160019178Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: July 27, 2015Publication date: January 21, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9128818Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: May 23, 2014Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9037548Abstract: A networked data storage system includes data movement logic and a virtual machine for executing a data management processing plan which is generated by a facility outside the storage array based on statistical information associated with extent level activity metrics provided by the storage array. Dynamically updated and automatically generated data management processing plans are provided to the storage array in the form of units of compiled byte code which the storage array is able to verify and execute using a virtual machine. The virtual machine interfaces with the environment in which it is embedded in a carefully constrained manner, thereby preventing clearly undesirable operations.Type: GrantFiled: June 30, 2011Date of Patent: May 19, 2015Assignee: EMC CorporationInventors: Sean Christopher Dolan, Marik Marshak, Alexandr Veprinsky, Owen Martin, Xiaomei Liu, Hui Wang
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Publication number: 20150081999Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: May 23, 2014Publication date: March 19, 2015Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 8738886Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.Type: GrantFiled: February 17, 2004Date of Patent: May 27, 2014Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20140038294Abstract: Systems and methods are provided for defining a nucleic acid construct for integration at locus L of an organism. Nucleic acid requests are received, each such request specifying a genetic change to L. The request are expanded into component polynucleotides which are then arranged into {AR1, . . . , ARm} different arrangements, each ARi in {AR1, . . . , ARm} defining a different arrangement of the component polynucleotides. A score Si for each ARi in {AR1, . . . , ARm} is determined based on whether source constructs encoding a portion of ARi are physically present. An ARf in {AR1, . . . , ARm} is selected based on the score for ARf. Primer pairs are calculated to amplify the portions of ARf not represented in the source constructs. The portions of ARf amplified by the primer pairs and the portions of ARf in the source constructs, ordered by ARf, define the nucleic acid construct.Type: ApplicationFiled: October 11, 2012Publication date: February 6, 2014Applicant: Amyris Biotechnologies, Inc.Inventors: Darren M. Platt, Michael W. Bissell, Sunil S. Chandran, Brian L. Hawthorne, Erik Jedediah Dean, Christopher Dolan
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Patent number: 8343077Abstract: An oral function and dysfunction quantification device that automatically records the amount of time required for a laboratory animal to gnaw through multiple obstructions in a tube comprising a confinement tube and spring-loaded polymer dowels that actuate timers to precisely record the time required for a rodent to complete a discrete gnawing task. The investigation of human orofacial pain requires an animal test that objectively measures impairment secondary to pain during an oral function (gnawing) that is analogous to behavior that elicits pain in human patients (chewing). The device can also evaluate behavioral change secondary to complex disorders such as anxiety and depression and facilitate evaluation of molecular mechanisms and pharmacologic therapies relevant to chronic orofacial pain and behavioral disorders.Type: GrantFiled: February 11, 2009Date of Patent: January 1, 2013Inventors: John Christopher Dolan, Brian Lee Schmidt
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Patent number: 8332160Abstract: Systems and methods are provided for defining a nucleic acid construct for integration at locus L of an organism. Nucleic acid requests are received, each such request specifying a genetic change to L. The request are expanded into component polynucleotides which are then arranged into {AR1, . . . , ARm} different arrangements, each ARi in {AR1, . . . , ARm} defining a different arrangement of the component polynucleotides. A score Si for each ARi in {AR1, . . . , ARm} is determined based on whether source constructs encoding a portion ofARi are physically present. An ARf in {AR1, . . . , ARm} is selected based on the score for ARf. Primer pairs are calculated to amplify the portions of ARf not represented in the source constructs. The portions of ARf amplified by the primer pairs and the portions of ARf in the source constructs, ordered by ARf, define the nucleic acid construct.Type: GrantFiled: April 9, 2012Date of Patent: December 11, 2012Assignee: Amyris Biotechnologies, Inc.Inventors: Darren M. Platt, Michael W. Bissell, Sunil S. Chandran, Brian L. Hawthorne, Erik Jedediah Dean, Christopher Dolan
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Publication number: 20060243258Abstract: An engine has a housing and a working member movable within an interior of the housing and separating a combustion chamber from a non-combustion chamber. Additionally, the engine may include a chamber-ventilation system that may include a passageway with a first end of the passageway connected to the non-combustion chamber and a second end of the passageway located downstream of the first end of the passageway. The chamber-ventilation system may further include a filter system disposed within the passageway. The filter system may include a filter housing and a filter disposed in the filter housing. Additionally, the chamber-ventilation system may be configured such that, during operation of the engine, gas travels from the non-combustion chamber, into the first end of the passageway, through the passageway, to the second end of the passageway.Type: ApplicationFiled: April 28, 2005Publication date: November 2, 2006Inventors: Michael Withrow, Seth Slaughter, Christopher Dolan, Bryant Richie
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Publication number: 20040186921Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.Type: ApplicationFiled: February 17, 2004Publication date: September 23, 2004Applicant: Intel Corporation, a California corporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 6694380Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.Type: GrantFiled: December 27, 1999Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta