Patents by Inventor Christopher E. Cox

Christopher E. Cox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11377438
    Abstract: Novel compounds of the structural formula (I), and the pharmaceutically acceptable salts thereof, are inhibitors of Nav1.8 channel activity and may be useful in the treatment, prevention, management, amelioration, control and suppression of diseases mediated by Nav1.8 channel activity. The compounds of the present invention may be useful in the treatment, prevention or management of pain disorders, cough disorders, acute itch disorders, and chronic itch disorders.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: July 5, 2022
    Assignee: Merck Sharp & Dohme LLC
    Inventors: Ashok Arasappan, Ian M. Bell, Michael J. Breslin, Christopher James Bungard, Christopher S. Burgey, Harry R. Chobanian, Jason M. Cox, Anthony T. Ginnetti, Deodial Guy Guiadeen, Kristen L. G. Jones, Mark E. Layton, Hong Liu, Jian Liu, James J. Perkins, Shawn J. Stachel, Linda M. Suen-Lai, Zhe Wu
  • Publication number: 20220189532
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Bill NALE, Christopher E. COX
  • Publication number: 20220157374
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Inventors: Christopher E. COX, Bill NALE
  • Patent number: 11335395
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale
  • Publication number: 20220121392
    Abstract: An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventors: Christopher E. Cox, Christopher P. Mozak
  • Patent number: 11282561
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 11276453
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Bill Nale
  • Patent number: 11226762
    Abstract: An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Christopher E. Cox, Christopher P. Mozak
  • Patent number: 11093391
    Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Saher Abu Rahme, Christopher E. Cox, Joydeep Ray
  • Publication number: 20210247919
    Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
    Type: Application
    Filed: April 2, 2021
    Publication date: August 12, 2021
    Inventors: Dean-Dexter R. EUGENIO, Arvind KUMAR, John R. GOLES, Christopher E. COX
  • Publication number: 20210232504
    Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Inventors: James A. BOYD, Christopher E. COX, Nikhil TALPALLIKAR
  • Patent number: 11074959
    Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: James A. McCall, Christopher P. Mozak, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang
  • Patent number: 11061590
    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Christopher P. Mozak, Christopher E. Cox
  • Patent number: 11042315
    Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Christopher E. Cox, Navneet Dour, Asaf Rubinstein, Israel Diamand
  • Publication number: 20210151095
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 20, 2021
    Inventors: Bill NALE, Christopher E. COX
  • Patent number: 10969979
    Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Dean-Dexter R. Eugenio, Arvind Kumar, John R. Goles, Christopher E. Cox
  • Patent number: 10950288
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 10938161
    Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Jaejin Lee, Jun Liao, Xiang Li, Christopher E. Cox
  • Patent number: 10923859
    Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Jaejin Lee, Jun Liao, Xiang Li, George Vergis, Christopher E. Cox
  • Publication number: 20210020224
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Application
    Filed: October 2, 2020
    Publication date: January 21, 2021
    Inventors: Christopher E. COX, Kuljit S. BAINS, Christopher P. MOZAK, James A. McCALL, Akshith VASANTH, Bill NALE