Abstract: A mine neutralizing device that includes a buoy. The buoy includes a mine neutralizing device capable of swimming to an undersea mine to neutralize it. A method for neutralizing undersea mines includes locating an undersea mine, placing a buoy containing a mine neutralizer near the mine, and swimming the mine neutralizer to the undersea mine.

Abstract: A mine neutralizing device that includes a buoy. The buoy includes a mine neutralizing device capable of swimming to an undersea mine to neutralize it. A method for neutralizing undersea mines includes locating an undersea mine, placing a buoy containing a mine neutralizer near the mine, and swimming the mine neutralizer to the undersea mine.

Abstract: A mine neutralizing device that includes a buoy. The buoy includes a mine neutralizing device capable of swimming to an undersea mine to neutralize it. A method for neutralizing undersea mines includes locating an undersea mine, placing a buoy containing a mine neutralizer near the mine, and swimming the mine neutralizer to the undersea mine.

Abstract: The decoder herein described recovers the clocking and the data in a binary format from a three level coded signal. The decoder has application to data rates in excess of one half gigabits per second, which are common to optical communication channels. The decoder employs a comparator for evaluating to two bit accuracy each state of the signal, a two stage, two bit per stage shift register, and decision logic for recovering the data in a binary format. The decoder is monolithically integrated using buffered FET logic on a gallium arsenide substrate. In the decoder, the comparator is optimized by the use of three zero crossing detectors, one of which has a zero input for reference purposes, in combination with two internal voltage dividers and two external voltage references for achieving an accurate drift free determination of the levels of the three level code (TLC) signal.

Abstract: The present invention relates to pipeline processors having testing means for identifying malfunctioning modules and for testing the self-testing means themselves. The testing employs the parity check principle and provides an on-line test of memory modules and an off-line test at the processor clock rate of both memory and arithmetic modules. The means for testing include a parity encoder associated with each module and a comparator which couples parity "comparison values" to a priority encoder, operating at the high speed clock rate of the pipeline processor. The test results are then supplied to a RAM, also operating at the clock rate of the pipeline processor. With the test results in the memory, a microcomputer is provided to search the memory at a slower rate for the highest priority failed module.