Abstract: A system for using OCR processing to read human readable characters that correspond to an unsuccessfully decoded code word in a bar code symbol. An imaging system captures an image of a label that includes a bar code symbol and corresponding human readable characters. The system attempts to decode the bar code symbol by decoding each of the constituent bar code characters. If a bar code characters is not successfully decoded, the system locates the associated human readable text and segments the text into individual character images. The unsuccessfully decoded bar code character is mapped to one or more of the alphanumeric character images, which are converted into text characters. The resulting ASCII data is used to create a substitute bar code character in the bar code symbology. After the bar code symbol is decoded using the substitute bar code character, the symbol is validated through check summing or other means.

Abstract: A bar code reader decodes a bar code symbol in a pixel image by transforming the data corresponding to the symbol along a first scan line, where the transformation comprises rotation and stretching. The reader generates a composite vector and a count vector from the transformed data. The reader then transforms (by rotating and stretching) another set of data corresponding to the symbol along a second scan line. The reader updates the composite and count vectors using the second set of transformed data. The reader then generates a one-dimensional composite signal from the composite and count vectors. The reader decodes the symbol by decoding the composite signal.

Abstract: A method and system for updating the logical address of pointers used by a processor in a paged memory organization. A logical address associative memory provides a cache holding data about a paged segment of data words eliminating the need to fetch the data from main memory. Update index logic and insertion logic operate to update the logical address of an original pointer to indicate the logical next address of new data sought from main memory. The system is specifically designed to expedite the situation where the page referenced by the next address is different from that referenced by the original pointer's address.

Abstract: An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical base address and page index of the targeted word resides in an associated set of CAMs and RAMs. If the targeted word's logical base address and page index is not in the set of associated CAMs and RAMs, this information can be acquired at the most optimum rate for enabling data access. This rate may require several clock cycles.

Abstract: A system for updating logical address data in pointers used by a processor in a computer system using paged memory. An Actual Segment Descriptor Associative Memory System (ASDAM) provides a dual cache memory for searching page table logical addresses and page index values which can, if available, provide a logical address, via a logical address RAM, to update a pointer in one machine cycle, with a new logical address. If the required data is not available in the dual cache memory, then other circuitry is operative to translate logical addresses into physical addresses permitting rapid access to main memory in order to supply the dual cache memory and logical address RAM with the required data.

Abstract: A bar code reader decodes a bar code symbol in a pixel image by transforming the data corresponding to the symbol along a first scan line, where the transformation comprises rotation and stretching. The reader generates a whitening gradient vector, a blackening gradient vector, and a count vector from the transformed data. The reader then transforms (by rotating and stretching) another set of data corresponding to the symbol along a second scan line. The reader updates the whitening and blackening gradient vectors and the count vector using the second set of transformed data. The reader then generates whitening and blackening gradient signals from the whitening and blackening gradient vectors and the count vector. The reader segments the whitening and blackening gradient signals and generates a single one-dimensional reconstructed signal based on the weighted centroids of the two segmented gradient signals. The reader then decodes the symbol by decoding the reconstructed signal.

Abstract: A bar code reader locates and decodes a bar code symbol in a pixel image by searching along a selected scan line for a candidate quiet zone and then counting the bright/dark transitions that correspond to candidate bars and spaces. The reader determines whether the candidate quiet zone and candidate bars and spaces correspond to a bar code symbol, and, if so, decodes the symbol. When processing binary pixel images, the reader searches for candidate quiet zones and counts bright/dark transitions by analyzing the image one byte of pixels at a time.

Abstract: A bar code reader decodes a bar code symbol in a pixel image by transforming the data corresponding to the symbol along a first scan line, where the transformation comprises rotation and stretching. The reader generates a composite vector and a count vector from the transformed data. The reader then transforms (by rotating and stretching) another set of data corresponding to the symbol along a second scan line. The reader updates the composite and count vectors using the second set of transformed data. The reader then generates a one-dimensional composite signal from the composite and count vectors. The reader decodes the symbol by decoding the composite signal.

Abstract: An alternate path selection structure is provided which reduces the effects of aborting an operation. The present invention comprises a structure and method that allows efficient retrieval of alternate paths to pursue in a microcode sequence.

Abstract: A bar code reader decodes a bar code symbol, one character at a time, by analyzing the spaces of each character independently from the bars of each character. The reader determines the widths of each space and each bar. The reader then determines a space-width threshold based on the widths of the spaces and a bar-width threshold based on the widths of the bars. The reader then classifies each space as being either narrow or wide by comparing each space to the space-width threshold. The reader also classifies each bar as being either narrow or wide by comparing each bar to the bar-width threshold. The reader then decodes the character according to the narrow/wide classifications.

Abstract: An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.