Abstract: A system determines a baseline cyberthreat-risk score for a user, and displays the baseline cyberthreat-risk score via a user interface. The system presents at least one cyberthreat-education activity via the user interface, and receives, via the user interface, at least one user input associated with the presented at least one cyberthreat-education activity. The system generates an updated cyberthreat-risk score at least in part by updating the baseline cyberthreat-risk score based at least in part on the user input, and displays the updated cyberthreat-risk score via the user interface.

Abstract: An interchangeable electro-mechanical lock core for use with a lock device having a locked state and an unlocked state is disclosed. The interchangeable electromechanical lock core may include a moveable plug having a first position relative to a lock core body which corresponds to the lock device being in the locked state and a second position relative to a lock core body which corresponds to the lock device being in the unlocked state.

Abstract: A system for remotely retrieving sensed conditions at one or more building components. The building components are remote or numerous so that a wireless collection of the sensed conditions provides a significant benefit to a builder or building operator. A remote transceiver sends a wireless signal to a building component. The building component includes an onboard transceiver. At least some of the energy from the transmitted wireless signal is received by the onboard transceiver, sent to a storage device, and stored therein. The stored energy is used to operate a sensor for sensing an onboard condition. The onboard condition is then wirelessly transmitted by the onboard transceiver back to the remote transceiver to be displayed.

Abstract: A unique point absorber type wave energy conversion device is disclosed that includes a Power Take Off (PTO) which uses a torsion spring to return a vertical shaft to its original position after being rotated by a rope or cord that pulls a reel via a guide system. This spring return allows the PTO and housing to stay stationary under the wave energy while a buoy at the surface provides an oscillating linear movement. The oscillating rotary motion caused by the interaction of the buoy and spring is converted into a one directional motion via a one-way clutch and is transmitted to generators using a gearbox that increases rotational speed.

Abstract: A system determines a baseline cyberthreat-risk score for a user, and displays the baseline cyberthreat-risk score via a user interface. The system presents at least one cyberthreat-education activity via the user interface, and receives, via the user interface, at least one user input associated with the presented at least one cyberthreat-education activity. The system generates an updated cyberthreat-risk score at least in part by updating the baseline cyberthreat-risk score based at least in part on the user input, and displays the updated cyberthreat-risk score via the user interface.

Abstract: A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Abstract: Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Abstract: Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Abstract: A pipelined x86 processor implements a method of detecting self-modifying code in which a prefetched block of instruction bytes may contain an instruction that is modified by a store instruction preceding it in the execution pipeline. The processor includes a Prefetch unit having a multi-block prefetch buffer, a Branch unit with a branch target cache (BTC), and a Load/Store (LDST) unit having store reservation stations.

Abstract: A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction.

Abstract: A pipelined 32 bit x86 processor including a prefetch unit and a branch unit. During sequential prefetching, the prefetch unit increments a prefetch physical address PFPA and a corresponding prefetch linear address PFLA--for each prefetch address, the PFLA is compared with the code segment limit linear address CSLA to determine if the corresponding prefetch block of 16 instruction bytes (cache line) contains the segment limit. If a COF hits in the branch unit, it outputs corresponding target address information used to generate a prefetch address--this target address information includes bits ?11:0! of the target address (which are the same for the target physical address), i.e., the branch unit does not provide a full PFLA for comparison with the CSLA.

Abstract: A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.