Patents by Inventor Christopher Edward Koob
Christopher Edward Koob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160246534Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.Type: ApplicationFiled: February 20, 2015Publication date: August 25, 2016Inventors: Christopher Edward KOOB, Erich James PLONDKE, Jiajin TU
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Publication number: 20160246731Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.Type: ApplicationFiled: February 20, 2015Publication date: August 25, 2016Inventors: Christopher Edward KOOB, Erich James PLONDKE, Jiajin TU
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Publication number: 20160239060Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: Christopher Edward Koob, Xufeng Chen, Robert Allan Lester, Manojkumar Pyla, Peixin Zhong
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Publication number: 20160092238Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Lucian CODRESCU, Christopher Edward KOOB, Eric Wayne MAHURIN, Suresh Kumar VENKUMAHANTI
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Patent number: 9239799Abstract: A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.Type: GrantFiled: June 26, 2008Date of Patent: January 19, 2016Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Christopher Edward Koob
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Patent number: 8995207Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.Type: GrantFiled: August 12, 2011Date of Patent: March 31, 2015Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Jen Tsung Lin, Manojkumar Pyla, Martin Saint-Laurent
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Patent number: 8943293Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.Type: GrantFiled: March 19, 2014Date of Patent: January 27, 2015Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
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Publication number: 20140281332Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius, Lucian Codrescu
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Publication number: 20140282508Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
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Publication number: 20140208027Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.Type: ApplicationFiled: March 19, 2014Publication date: July 24, 2014Applicant: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
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Patent number: 8719503Abstract: A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.Type: GrantFiled: June 25, 2012Date of Patent: May 6, 2014Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
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Patent number: 8656137Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.Type: GrantFiled: September 1, 2011Date of Patent: February 18, 2014Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Lucian Codrescu, Erich James Plondke, Bryan C. Bayerdorffer
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Publication number: 20130304994Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.Type: ApplicationFiled: May 8, 2012Publication date: November 14, 2013Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Suresh K. Venkumahanti
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Publication number: 20130282987Abstract: Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Dana M. Vantrease
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Publication number: 20130185511Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.Type: ApplicationFiled: May 14, 2012Publication date: July 18, 2013Applicant: QUALCOMM IncorporatedInventors: Peter G. Sassone, Christopher Edward Koob, Dana M. Vantrease, Suresh K. Venkumahanti, Lucian Codrescu
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Publication number: 20130061020Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.Type: ApplicationFiled: September 1, 2011Publication date: March 7, 2013Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Lucian Codrescu, Erich James Plondke, Bryan C. Bayerdorffer
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Publication number: 20130039133Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Jen Tsung Lin, Manojkumar Pyla, Martin Saint-Laurent
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Patent number: 8341353Abstract: A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.Type: GrantFiled: January 14, 2010Date of Patent: December 25, 2012Assignee: QUALCOMM IncorporatedInventors: Suresh K. Venkumahanti, Christopher Edward Koob, Lucian Codrescu
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Publication number: 20120265943Abstract: A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.Type: ApplicationFiled: June 25, 2012Publication date: October 18, 2012Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
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Patent number: 8266409Abstract: In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.Type: GrantFiled: March 3, 2009Date of Patent: September 11, 2012Assignee: QUALCOMM IncorporatedInventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen