Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.

Abstract: An embodiment may include circuitry to determine, at least in part, whether one or more reference patterns are present in a data stream in a packet flow. The circuitry may include first pattern matching circuitry communicatively coupled to second pattern matching circuitry. The first pattern matching circuitry may determine, based at least in part upon one or more deterministic pattern matching operations, whether at least one portion of the one or more reference patterns is present in the stream. If the first pattern matching circuitry determines that the at least one portion of the one or more reference patterns is present in the stream, the second pattern matching circuitry may determine, based at least in part upon one or more pattern matching threads, whether at least one other portion of the one or more reference patterns is present in the stream. Many modifications are possible without departing from this embodiment.

Abstract: Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.

Abstract: An embodiment may include circuitry to determine, at least in part, based at least in part upon history information, whether one or more reference patterns are present in a data stream in a packet flow. The data stream may span at least one packet boundary in the packet flow. The history information may include a beginning portion of a packet in the data stream, an ending portion of the packet, and another portion of the data stream. The circuitry may overwrite the another portion of the history information with a respective portion of the data stream to be examined by the circuitry depending, at least in part, upon whether the circuitry determines, at least in part, whether the one or more reference patterns are present in the data stream. The respective portion may be relatively closer than the another portion is to a beginning of the data stream.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract: A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.