Patents by Inventor Christopher Gonzalez
Christopher Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129293Abstract: Techniques for (i) using contextual information associated with an exposed credential to identify a resource that could be accessed using the exposed credential, (ii) identifying a responsible entity of that resource, and (iii) alerting the responsible entity about the exposed credential are disclosed. A credential is determined to be in an exposed state. The exposed credential, if used, could potentially provide an actor access to a resource, despite the fact that the actor should not have access to the resource. The exposed credential is analyzed to determine a context. Based on that context, the resource is identified. A responsible entity associated with the resource is identified. An alert is then sent to that entity.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Inventors: Michael Christopher FANNING, Suvam MUKHERJEE, Jacek Andrzej CZERWONKA, Christopher Michael Henry FAUCON, Eddy Toshiyuki OKADA NAKAMURA, Danielle Nicole GONZALEZ, Nicolas Yves Couraud, Alison Lynne MACLELLAN
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Patent number: 11906570Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: GrantFiled: April 6, 2023Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Patent number: 11754615Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: GrantFiled: September 21, 2021Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Publication number: 20230252218Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.Type: ApplicationFiled: February 8, 2022Publication date: August 10, 2023Inventors: BRIAN VERAA, Ryan Michael Kruse, Christopher Gonzalez, David Wolpert
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Publication number: 20230251299Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: ApplicationFiled: April 6, 2023Publication date: August 10, 2023Inventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Publication number: 20230086010Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Patent number: 11586798Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level.Type: GrantFiled: August 13, 2021Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Brian Veraa, David Wolpert, Ryan Michael Kruse, Christopher Gonzalez
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Publication number: 20230048541Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Brian Veraa, David Wolpert, Ryan Michael Kruse, Christopher Gonzalez
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Publication number: 20230031457Abstract: Methods, systems, apparatus, and articles of manufacture to crimp a tube are disclosed. An example crimp disclosed herein includes a first crimp section extending between a first end of the crimp and a point along the crimp between the first end and a second end, a first inner diameter of the first crimp section constant between the first end and the point, and a second crimp section adjacent the first crimp section, the second crimp section extending between the point and the second end, a second inner diameter of the second crimp section to increase from the point to the second end.Type: ApplicationFiled: September 30, 2022Publication date: February 2, 2023Inventors: Phil Geng, Ralph Miele, Christopher Gonzalez, Timothy Gates, Sanjoy Saha, Ashish Gupta, Sandeep Ahuja
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Patent number: 10776113Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: GrantFiled: June 21, 2019Date of Patent: September 15, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 10628158Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: GrantFiled: November 29, 2017Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 10579387Abstract: Technical solutions are described for executing one or more out-of-order (OoO) instructions by a processing unit. The execution includes detecting, by a load-store unit (LSU), a load-hit-store (LHS) in an out-of-order execution of the instructions, the detecting based only on effective addresses. The detecting includes determining an effective address associated with an operand of a load instruction. The detecting further includes determining whether a store instruction entry using said effective address to store a data value is present in a store reorder queue, and indicating that an LHS has been detected based at least in part on determining that store instruction entry using said effective address is present in the store reorder queue. In response to detecting the LHS, a store forwarding is performed that includes forwarding data from the store instruction to the load instruction.Type: GrantFiled: October 6, 2017Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 10534616Abstract: Technical solutions are described for executing one or more out-of-order instructions by a load-store unit (LSU) by detecting a load-hit-load (LHL) case based only on effective addresses (EA). An example method includes, in response to receiving a first load instruction, creating an entry in a LHL table. Further, in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second EA used by the second load instruction matching the predetermined number of bits from the first EA, comparing the first EA and the second EA. Further, a first thread identifier for the first load instruction is compared with a second thread identifier for the second load instruction. In response to the first EA matching the second EA, and the first thread identifier matching the second thread identifier, the method includes flushing the first load instruction.Type: GrantFiled: October 6, 2017Date of Patent: January 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190310849Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 10394558Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: GrantFiled: October 6, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108024Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108028Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.Type: ApplicationFiled: November 29, 2017Publication date: April 11, 2019Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108031Abstract: Technical solutions are described for executing one or more out-of-order (OoO) instructions by a processing unit. The execution includes detecting, by a load-store unit (LSU), a load-hit-store (LHS) in an out-of-order execution of the instructions, the detecting based only on effective addresses. The detecting includes determining an effective address associated with an operand of a load instruction. The detecting further includes determining whether a store instruction entry using said effective address to store a data value is present in a store reorder queue, and indicating that an LHS has been detected based at least in part on determining that store instruction entry using said effective address is present in the store reorder queue. In response to detecting the LHS, a store forwarding is performed that includes forwarding data from the store instruction to the load instruction.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108035Abstract: Technical solutions are described for executing one or more out-of-order instructions by a load-store unit (LSU) by detecting a load-hit-load (LHL) case based only on effective addresses (EA). An example method includes, in response to receiving a first load instruction, creating an entry in a LHL table. Further, in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second EA used by the second load instruction matching the predetermined number of bits from the first EA, comparing the first EA and the second EA. Further, a first thread identifier for the first load instruction is compared with a second thread identifier for the second load instruction. In response to the first EA matching the second EA, and the first thread identifier matching the second thread identifier, the method includes flushing the first load instruction.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 7949628Abstract: The described embodiments contemplate a system, method and computer-readable medium with computer-executable instructions for managing an information technology network. The novel system includes a network of data sources and a federated configuration management database capable of communicating with the data sources. The data sources also may be federated. The federated configuration database management identifies among the data sources. The system also includes a core database that is capable of communicating with the federated configuration management database. The core database defines relationships of the data sources with a business practice.Type: GrantFiled: December 29, 2005Date of Patent: May 24, 2011Assignee: United Services Automobile Association (USAA)Inventors: Mark Charles Blazek, Richard Christopher Gonzalez