Abstract: A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals.

Abstract: Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

Abstract: The present invention embodiments consolidate process control for a process including a plurality of control threads each associated with a stage of the process. A plurality of the control threads are analyzed to enable the process control with a reduced quantity of the control threads. Data associated with the plurality of control threads are validated and provided in a desired form. At least one parameter of each of the plurality of control threads is statistically analyzed to form at least one thread group including a plurality of the control threads satisfying the parameter analysis. Each thread group functions as a common thread to enable the process control with a reduced quantity of control threads. The present invention embodiments further include a method and program product apparatus for consolidating the process control.

Abstract: A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension scanning electron microscope (CDSEM). The present invention provides an image quality monitor that utilizes image processing and optimization to maintain image quality at a desired level. Images from a stage sample are automatically collected, while microscope operational parameters are determined based on image processing to enable continuous monitoring of microscope operation. The technique may be performed manually or automatically and generates set points for beam conditioning elements to produce or maintain ideal beam conditions to enhance image quality. The present invention generates data indicating optimized values for each beam alignment parameter. The optimized values are applied to the internal microscope values to optimize the beam.

Abstract: A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable fabrication of a semiconductor device, predicting overlay offset corrections based on one or more factors involved in the processing of the wafer, and utilizing the predicted overlay offset corrections to positionally control the lithographic tool.

Abstract: A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension scanning electron microscope (CDSEM). The present invention provides an image quality monitor that utilizes image processing and optimization to maintain image quality at a desired level. Images from a stage sample are automatically collected, while microscope operational parameters are determined based on image processing to enable continuous monitoring of microscope operation. The technique may be performed manually or automatically and generates set points for beam conditioning elements to produce or maintain ideal beam conditions to enhance image quality. The present invention generates data indicating optimized values for each beam alignment parameter. The optimized values are applied to the internal microscope values to optimize the beam.

Abstract: The disclosed system and method relates to the prediction of processing tool control parameters, i.e. controller state, for a particular processing tool, which has little or no utilization history, i.e. is data starved or has not gone through the learning curve, for a given process, or has undergone an event for which the current controller state has been reset or is otherwise now sub-optimal. The prediction is based on the processing tool control parameters of a substantially similar processing tool, being used in a substantially similar fashion to the given situation, which has significant utilization history. The processing tool having significant utilization history may be the same processing tool as the processing tool with little or no processing history where a manufacturing event disrupts the operations thereof. In this case, the pre-event control parameters and utilization history may be used, according to the disclosed embodiments, to predict the post-event controller state.

Abstract: A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable fabrication of a semiconductor device, predicting overlay offset corrections based on one or more factors involved in the processing of the wafer, and utilizing the predicted overlay offset corrections to positionally control the lithographic tool.

Abstract: The disclosed system and method relates to the prediction of processing tool control parameters, i.e. controller state, for a particular processing tool, which has little or no utilization history, i.e. is data starved or has not gone through the learning curve, for a given process, or has undergone an event for which the current controller state has been reset or is otherwise now sub-optimal. The prediction is based on the processing tool control parameters of a substantially similar processing tool, being used in a substantially similar fashion to the given situation, which has significant utilization history. The processing tool having significant utilization history may be the same processing tool as the processing tool with little or no processing history where a manufacturing event disrupts the operations thereof. In this case, the pre-event control parameters and utilization history may be used, according to the disclosed embodiments, to predict the post-event controller state.

Abstract: A system for maintaining the focus of an exposure tool includes an exposure tool and an analysis system. The exposure tool is configured to generate a sample for determining a product best center of focus, generate a first sample for determining an initial exposure tool focus, and generate a second sample for determining a second exposure tool focus. The analysis system is configured to determine an exposure tool delta baseline based on the product best center of focus and the initial exposure tool focus, set the exposure tool focus to the product best center of focus, determine a recommended focus based on the delta baseline and the second exposure tool focus, and set the exposure tool focus based on the recommended focus.

Abstract: In an overlay measurement mark comprising an inner box and an outer box located at a predetermined area on a mask through which patterns are formed on a semiconductor device, the improvement of an overlay mark that extends the overlay measurement range comprising: in-focused marks means printed at an optimal or ideal focal plane level from an illumination source, and de-focused marks means located at a different focus level from the optimal focal plane to provide image placement shift of the de-focused marks larger than that of the in-focused marks means to enable measurement of the shift of de-focused marks that are not attributable to a mechanical alignment error to be determined with greater accuracy.