Patents by Inventor Christopher H. Olson
Christopher H. Olson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969344Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve to a deficient valve. In one embodiment, for instance, a support structure and an expandable prosthetic valve are advanced through the aortic arch of a patient using a delivery system. The support structure is delivered to a position on or adjacent to the surface of the outflow side of the aortic valve (the support structure defining a support-structure interior). The expandable prosthetic valve is delivered into the aortic valve and into the support-structure interior. The expandable prosthetic heart valve is expanded while the expandable prosthetic heart valve is in the support-structure interior and while the support structure is at the position on or adjacent to the surface of the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the support structure and the expanded prosthetic heart valve.Type: GrantFiled: December 9, 2019Date of Patent: April 30, 2024Assignee: EDWARDS LIFESCIENCES CORPORATIONInventors: Christopher J. Olson, Glen T. Rabito, Dustin P. Armer, Minh T. Ma, Devin H. Marr, Cheng-Tung Huang, Hiroshi Okabe, Kevin M. Stewart, Alison S. Curtis, Philip P. Corso, Jr.
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Patent number: 10353670Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.Type: GrantFiled: July 27, 2017Date of Patent: July 16, 2019Assignee: Oracle International CorporationInventors: Jeffrey S. Brooks, Christopher H. Olson, Hesam Fathi Moghadam, Josephus C. Ebergen
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Patent number: 10180819Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.Type: GrantFiled: October 26, 2016Date of Patent: January 15, 2019Assignee: Oracle International CorporationInventors: Jeffrey S. Brooks, Christopher H. Olson, Eugene Karichkin
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Publication number: 20180329686Abstract: The disclosed embodiments relate to the design of an integer division circuit, which comprises: a dividend-input that receives an integer dividend A; a divisor-input that receives an integer divisor B; a quotient-output that outputs an integer quotient q; and a division engine that executes the Goldschmidt method to divide A by B to produce q. During a pre-processing operation, which commences executing before the Goldschmidt method starts executing, the division engine determines whether A<B. If A<B, the division engine sets q=0 without having to execute the Goldschmidt method.Type: ApplicationFiled: November 17, 2017Publication date: November 15, 2018Applicant: Oracle International CorporationInventors: Jo C. Ebergen, Dmitry Ju Nadezhin, Christopher H. Olson, Jeffrey S. Brooks
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Publication number: 20170322768Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.Type: ApplicationFiled: July 27, 2017Publication date: November 9, 2017Inventors: Jeffrey S. Brooks, Christopher H. Olson, Hesam Fathi Moghadam, Josephus C. Ebergen
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Patent number: 9747073Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.Type: GrantFiled: March 6, 2014Date of Patent: August 29, 2017Assignee: Oracle International CorporationInventors: Jeffrey S Brooks, Christopher H Olson, Hesam Fathi Moghadam, Josephus C Ebergen
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Publication number: 20170046128Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Inventors: Jeffrey S. Brooks, Christopher H. Olson, Eugene Karichkin
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Patent number: 9507564Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.Type: GrantFiled: April 14, 2014Date of Patent: November 29, 2016Assignee: Oracle International CorporationInventors: Jeffrey S Brooks, Christopher H Olson, Eugene Karichkin
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Patent number: 9507656Abstract: A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.Type: GrantFiled: April 16, 2009Date of Patent: November 29, 2016Assignee: Oracle America, Inc.Inventors: Jeffrey S. Brooks, Paul J. Jordan, Christopher H. Olson
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Patent number: 9317286Abstract: A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.Type: GrantFiled: March 31, 2009Date of Patent: April 19, 2016Assignee: Oracle America, Inc.Inventors: Christopher H. Olson, Gregory F. Grohoski, Lawrence A. Spracklen
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Publication number: 20150378726Abstract: Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Christopher H. Olson, Jeffrey S. Brooks, Albert Danysh
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Publication number: 20150293747Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.Type: ApplicationFiled: April 14, 2014Publication date: October 15, 2015Inventors: Jeffrey S. Brooks, Christopher H. Olson, Eugene Karichkin
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Publication number: 20150254065Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Inventors: Jeffrey S. Brooks, Christopher H. Olson, Hesam Fathi Moghadam, Josephus C. Ebergen
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Patent number: 9086890Abstract: Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.Type: GrantFiled: January 6, 2012Date of Patent: July 21, 2015Assignee: Oracle International CorporationInventors: Christopher H. Olson, Jeffrey S. Brooks, Matthew B. Smittle
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Patent number: 8977670Abstract: Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.Type: GrantFiled: May 11, 2012Date of Patent: March 10, 2015Assignee: Oracle International CorporationInventors: Jeffrey S. Brooks, Christopher H. Olson
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Patent number: 8892622Abstract: A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.Type: GrantFiled: April 7, 2011Date of Patent: November 18, 2014Assignee: Oracle International CorporationInventors: Christopher H. Olson, Jeffrey S. Brooks
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Patent number: 8886920Abstract: A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.Type: GrantFiled: September 8, 2011Date of Patent: November 11, 2014Assignee: Oracle International CorporationInventors: Christopher H. Olson, Manish K. Shah
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Patent number: 8862861Abstract: Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes of the pipeline. In one embodiment, a misprediction bit is be used to indicate that a misprediction has occurred, and younger CTIs than the CTI that was mispredicted are suppressed. In some embodiments, the processor may be configured to execute instruction streams from multiple threads. Each thread may include a misprediction indication. CTIs in each thread may execute in program order with respect to other CTIs of the thread, while instructions other than CTIs may execute out of program order.Type: GrantFiled: September 8, 2011Date of Patent: October 14, 2014Assignee: Oracle International CorporationInventors: Christopher H. Olson, Manish K. Shah
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Patent number: 8832464Abstract: A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include hash instructions defined within the ISA. In addition, the hash instructions may be executable by the cryptographic unit to implement a hash that is compliant with one or more respective hash algorithm specifications. In response to receiving a particular hash instruction defined within the ISA, the cryptographic unit may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.Type: GrantFiled: March 31, 2009Date of Patent: September 9, 2014Assignee: Oracle America, Inc.Inventors: Christopher H. Olson, Jeffrey S. Brooks, Robert T. Golla
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Patent number: 8671129Abstract: A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products.Type: GrantFiled: March 8, 2011Date of Patent: March 11, 2014Assignee: Oracle International CorporationInventors: Jeffrey S. Brooks, Christopher H. Olson