Abstract: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output vector of the faulty hardware block, enables a software work-around for the new input vector, and accepts the software work-around input as the output vector of the programmable logic circuit. The feedforward LAM neural network checking circuit has a weight matrix whose elements are based on a set of known bad input vectors for said faulty hardware block. The feedforward LAM neural network checking circuit may update the weight matrix online using one or more additional bad input vectors. A discrete Hopfield algorithm is used to calculate the weight matrix W.

Abstract: Systems, methods, apparatus and software can be implemented to provide a debugger agent, either separate form or integrated into the script-based testing platform, to coordinate the selection, activation, and or/operation of debuggers suitable for a particular unit and program under test. Such a debugger agent can provide run time monitoring and debugging activities where previously not possible. The debugger agent is generally independent agent, in that it can work with a variety of types of test scripts, test script handlers, programming languages, and debuggers without customization. Moreover, implementation generally needs no code instrumentation.

Abstract: Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory leaks, and subsequent verification confirms whether the potential memory leaks are memory leaks.

Abstract: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output vector of the faulty hardware block, enables a software work-around for the new input vector, and accepts the software work-around input as the output vector of the programmable logic circuit. The feedforward LAM neural network checking circuit has a weight matrix whose elements are based on a set of known bad input vectors for said faulty hardware block. The feedforward LAM neural network checking circuit may update the weight matrix online using one or more additional bad input vectors. A discrete Hopfield algorithm is used to calculate the weight matrix W.