Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.

Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Abstract: According to an example embodiment, the present invention is directed to a CMP apparatus having a polishing table, a wafer carrier adapted to carry a wafer on a pad, and a conditioning wheel. If the pad is being polished in a center-fast or center-slow manner, the conditioning wheel is used to condition the pad and to improve the center-fast or center-slow condition. Benefits of using this embodiment include improved wafer quality, improved pad life, a reduction in defective wafers, and faster production.

Abstract: A method for polishing wafers includes providing a wafer having a process layer formed thereon; providing a polishing tool having a plurality of control zones and being adapted to polish the process layer based on an operating recipe, the operating recipe having a control variable corresponding to each of the control zones; measuring a pre-polish thickness profile of the process layer; comparing the pre-polish thickness profile to a target thickness profile to determine a desired removal profile; determining values for the control variables associated with the control zones based on the desired removal profile; and modifying the operating recipe of the polishing tool based on the values determined for the control variables. A processing line includes a polishing tool, a metrology tool, and a process controller. The polishing tool is adapted to polish a wafer having a process layer formed thereon based on an operating recipe.

Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

Abstract: Various methods of inspecting a film on a semiconductor workpiece for a residue are provided. In one aspect, a method of inspecting a film on a semiconductor workpiece wherein the film has a known infrared signature is provided. The method includes heating the workpiece so that the film emits infrared radiation and sensing the infrared radiation emitted from the film. The infrared signature of the radiation emitted from the film is compared with the known infrared signature and a signal indicative of a deviation between the infrared signature of the emitted infrared radiation and the known infrared signature is generated. The method enables the rapid and accurate detection of residues, such as oxide residues on nitride films.

Abstract: A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.

Abstract: A rotary chemical-mechanical polishing apparatus with multiple fluid-bearing platens for use in semiconductor fabrication is described together with a method for chemical-mechanical polishing of semiconductor substrates (“wafers”). A single polishing pad is affixed to a pad backing composed of a thin metal membrane. A polishing fluid is introduced onto an upper surface of the polishing pad. One or more wafers are held face down upon the upper surface of the polishing pad by carriers. Fluid-bearing platens are placed below a lower surface of the pad backing and located directly underneath each wafer. While polishing wafers, the polishing pad and pad backing are rotated about their common center, each carrier and wafer pair is rotated about its common center, the carriers apply a down force on the wafers, and the fluid-bearing platens support the pad backing. The fluid-bearing platens support the pad backing with a fluid flow that exerts a pressure on the pad backing.

Abstract: A polishing pad having a cross-sectional open area which varies with depth from the pad surface is provided. The cross-sectional open area of the pad may increase and/or decrease moving away from the outer pad surface. In some cases, the cross-sectional open area of the pad varies uniformly with depth over the entire pad. In other cases, certain regions of the pad may define local cross-sectional open areas which vary differently. This can, for example, allow the open area of the pad to vary with pad life and improve or tailor the polishing uniformity of the pad and/or extend the useful life of the pad.

Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

Abstract: A method of controlling surface non-uniformity of a process layer includes receiving a first lot of wafers, and polishing a process layer of the first lot of wafers. A control variable of the polishing operations is measured after the polishing is performed on the process layer. A first adjustment input for an arm oscillation length of a polishing tool is determined based on the measurement of the control variable. A process layer of a second lot of wafers is polished using the adjustment input for the arm oscillation length. A controller for controlling surface non-uniformity of a process layer includes an optimizer and an interface. The optimizer is adapted to determine a first adjustment input for arm oscillation length of a polishing tool based on a measurement of a control variable from a first lot of wafers. The interface is adapted to provide the first adjustment input to the polishing tool for polishing a second lot of wafers.

Abstract: A polishing assembly for CMP of semiconductors includes an air bearing platen having multiple concentric rings of air holes, with each ring defining an air delivery zone. Each ring includes air source holes alternating with air drain holes. A distribution plate is mated with the platen, and the distribution plate has alternating rings of air supply and air exhaust rings. The air supply rings include air supply apertures that are aligned with the air source holes in the platen, and the air exhaust rings include air exhaust apertures that are aligned with the air drain holes in the platen. With this structure, the air distribution profile of each air delivery zone can be established relatively independently of the profiles of the other zones.

Abstract: A polishing pad having a wear level indicator and a polishing system employing the same is provided. A polishing pad, in accordance with one embodiment of the invention, includes a pad structure and an indicator, disposed in the pad structure, indicating the wear level of the pad structure. The pad structure may, for example, include a top pad and a bottom pad with the indicator being disposed in the top pad. The wear level may, for example, be a critical thickness of the polishing pad which indicates the end of the pad lifetime or which indicates the need to change polishing processing. The use of a wear level indicator allows for efficient and reliable pad wear level indication.

Abstract: A method for measuring the planarization efficiency of a planarization process and a device for use with the method are provided. The device may be a substrate having a set of isolated features, such as trenches or hills, with different widths. In the method, a removable layer of material is formed over the substrate. The substrate features form corresponding features in the removable layer with varying dimensions. A pre-planarization thickness of the removable layer of material is measured at each feature and at one or more of isolation areas. The removable layer of material is then planarized using a planarization process associated with one or more process parameters. A post-planarization thickness of the removable is measured at each feature and at one or more of the isolation regions. The planarization efficiency of the planarization process is then determined as a function of the dimensions of the substrate features or corresponding features in the removable layers and/or one or more process parameters.