Abstract: A method for radar imaging is disclosed herein. The method may comprise using a plurality of radar antenna arrays provided on a terrestrial vehicle to obtain phase measurements associated with one or more radar signals transmitted and received by the plurality of radar antenna arrays as the terrestrial vehicle moves through an environment. The method may further comprise processing the phase measurements to compute (i) a set of object-specific properties for one or more objects external to the terrestrial vehicle and (ii) a set of vehicle-specific properties for the terrestrial vehicle. The method may further comprise using the set of object-specific properties and the set of vehicle-specific properties to generate one or more radar images of the environment as the terrestrial vehicle moves through the environment.

Abstract: A system for determining a spatial disposition or a characteristic of a target external to a terrestrial vehicle is provided. The system may comprise a radar antenna array comprising a transmitting antenna and a receiving antenna, a vehicle position sensor configured to obtain a spatial disposition of the terrestrial vehicle, and a controller operatively coupled to the radar antenna array and the vehicle position sensor. The controller can be configured to synchronize successive radar pulses transmitted by the transmitting antenna and a plurality of signals received by the receiving antenna, with the spatial disposition of the terrestrial vehicle obtained by the vehicle position sensor substantially in real time as the terrestrial vehicle is in motion, to generate a set of synchronized measurements, and use the set of synchronized measurements to determine (i) the spatial disposition of the target relative to the terrestrial vehicle or (ii) the characteristic of the target.

Abstract: Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

Abstract: Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

Abstract: A system for determining a spatial disposition or a characteristic of a target external to a terrestrial vehicle is provided. The system may comprise a radar antenna array comprising a transmitting antenna and a receiving antenna, a vehicle position sensor configured to obtain a spatial disposition of the terrestrial vehicle, and a controller operatively coupled to the radar antenna array and the vehicle position sensor. The controller can be configured to synchronize successive radar pulses transmitted by the transmitting antenna and a plurality of signals received by the receiving antenna, with the spatial disposition of the terrestrial vehicle obtained by the vehicle position sensor substantially in real time as the terrestrial vehicle is in motion, to generate a set of synchronized measurements, and use the set of synchronized measurements to determine (i) the spatial disposition of the target relative to the terrestrial vehicle or (ii) the characteristic of the target.

Abstract: A folding platform assembly for the top deck of motor vehicle carrier trucks. The platform features a grate, whereupon a person may safely and comfortably walk along the length of the truck. The platform also features a safety net system affixed to the grate to catch a person in the event of a slip, trip, or fall from the grate. The grate has an access panel for easy ingress and egress to the platform from a ladder or set of steps. When storing or transporting the platform, a folding mechanism pushes the platform into its closed, substantially-vertical position. This same mechanism pulls the platform into its open position when it is ready for use.

Abstract: A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

Abstract: A retracting platform assembly for motor vehicle carrier trucks, where the platform retracts to a vertical position. The railing system remains in a vertical position, extending and retracting along a horizontal plane, and provides additional protection from falling off the edge of the platform. A series of elevation rods between the platform grate and the railing system aids in the transition between the extended and retracted positions. A weight-bearing beam assists in supporting the weight of the platform assembly, as well as attaches to a power supply that pushes and pulls the platform assembly from one position to the other.

Abstract: A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

Abstract: The present invention provides modified oligonucleotide primers designed to incorporate a cleavable moiety so that a 3? portion of the primer (linked to an extension product) can be released from an upstream 5? portion of the primer. Upon selective cleavage of the cleavable site, primer extension products that contain about five or fewer base pairs of the primer sequence are released, to provide more useful sizing and sequence information per fragment than extension products containing the entire primer.

Abstract: This invention relates to methods for screening nucleic acids for mutations by analyzing nonrandomly fragmented nucleic acids using mass spectrometric techniques and to procedures for improving mass resolution and mass accuracy of these methods of detecting

Abstract: This invention relates to methods for screening nucleic acids for polymorphisms by analyzing amplified target nucleic acids using mass spectrometric techniques and to procedures for improving mass resolution and mass accuracy of these methods of detecting polymorphisms.

Abstract: The present invention provides modified oligonucleotide primers designed to incorporate a cleavable moiety so that a 3' portion of the primer (linked to an extension product) can be released from an upstream 5' portion of the primer. Upon selective cleavage of the cleavable site, primer extension products that contain about five or fewer base pairs of the primer sequence are released, to provide more useful sizing and sequence information per fragment than extension products containing the entire primer.

Abstract: The present invention provides modified oligonucleotide primers that (i) are designed for attachment to a solid support in a manner that does not block the ability to extend the primer from its 3' end, and (ii) incorporate a clearable moiety so that a 3' portion of the primer (linked to an extension product) can be released from an immobilized 5' portion. Upon selective cleavage of the cleavable site, a large portion of the primer fragment remains affixed to the solid support. This enables the release of primer extension products that contain about five or fewer base pairs of the primer sequence, to provide more useful sizing and sequence information per fragment than extension products containing the entire primer.

Abstract: A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.

Abstract: A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.