Abstract: Apparatuses, systems, and methods comprising acoustically absorptive air ducts comprising an internally positioned structure component as an endoskeleton and an air impervious inner layer, and an acoustically absorptive foam outer layer, environmental control systems comprising such air ducts, and vehicles incorporating such environmental control systems are disclosed with methods for manufacture and installations are disclosed.

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

Abstract: A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.

Abstract: In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.

Abstract: A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.

Abstract: A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add.

Abstract: A system and method for forwarding a first instruction into a second instruction in a processor is disclosed. The processor comprises an execution unit and providing a plurality of instructions. The first instruction depends upon execution of the second instruction but does not otherwise require execution by the execution unit. The method first searches for the second instruction. The method then forwards the first instruction via the second instruction by appending a tag to the second instruction, the tag identifying the first instruction.One aspect of the method and system forwards a store instruction into a floating point instruction in a processor. The store instruction has a source address and the floating point instruction has a target address. The processor provides a plurality of instructions. The method searches for the floating point instruction that is provided before the store instruction. The method then determines if the source address is equal to the target address.

Abstract: An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed.

Abstract: A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information.

Abstract: A distributed completion control system for a microprocessor is disclosed. The system comprises a plurality of dispatch units, each of the dispatch units further comprises a dispatch queue responsive to a fetched address for receiving instructions; a plurality of control dependent tags; and means for indicating that the control dependent tags have been assigned to the appropriate instructions. The system further includes a plurality of execution units for receiving the instructions and the control dependent tags.

Abstract: A timing driven placement system and method for designing an integrated circuit. The inventive method includes the steps of identifying a plurality of nets having blocks of circuit components connected by conductive elements and assigning weights to the nets in proportion to timing and resistive-capacitive (RC) effects therein. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.

Abstract: A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of the guard bit. Both aspects comprise means for providing an intermediate result of a floating point mathematical operation involving at least a first and a second operand and means for providing a mask indicating a position of a leading one in a mantissa of the intermediate result. In the first aspect, means for aligning a first bit of the mask to an (n+2)nd bit of the intermediate result, where n is the number of bits in a mantissa of the first or second operand, are coupled to the intermediate result providing means. In the second aspect, means for aligning a first bit of the mask to an (n+1)st bit of the intermediate result are coupled to the intermediate result providing means.

Abstract: A system and method for minimizing the delay associated with executing a register dependent instruction in which the execution of the register dependent instruction is dependent on an operand of a preceding instruction. In a branch unit for executing register dependent instructions, functional units are connected via a rename bus, and the functional units are connected to a general purpose register (GPR) via a GPR bus. The system and method routes the rename bus and the GPR bus directly to an instruction fetch address register thereby enabling the branch unit to execute a register dependent instruction during the same cycle as the preceding instruction.

Abstract: A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT.

Abstract: A system and method for calculating a floating point add/subtract of a plurality of floating point operands is disclosed. The system comprises at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path includes a first aligner, a first adder coupled to the first aligner, and a first normalizer coupled to the first adder. The first normalizer is capable of shifting a mantissa by a substantially smaller number of digits than the first aligner. The second data path comprises control logic, a second aligner coupled to the control logic, a second adder coupled to the second aligner, and a second normalizer coupled to the second adder. The control logic provides a control signal that is responsive to a first predetermined number of digits of each exponent of a pair of exponents. The pair of exponents are the exponents for a pair of inputs to the second data path.

Abstract: A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B mantissa. The shifter includes a sequential stack of multiplexers, typically three (3), for shifting the B mantissa to align it with the A*C product, and a complementer contained between two of the multiplexers to invert the signals when B is a negative number. A shift amount generator responsive to the A, B and C exponents produces control signals for the multiplexers. The shift amount generator includes a multiple input adder utilizing carry save adder and carry lookahead adder techniques to minimize delay, and separate decoders for each multiplexer or group of multiplexers. The generator also includes a Leading Zeros Anticipator (LZA) circuit for the most significant bits to limit shift amount signals that are within the shifting range of the shifter, which reduces the delay attributed to the carry lookahead adder.

Abstract: A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.