Patents by Inventor Christopher Hatem

Christopher Hatem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096602
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Patent number: 11862433
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 2, 2024
    Assignee: Varlan Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Publication number: 20210313154
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Patent number: 11069511
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 20, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Patent number: 10879055
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Kevin Anglin
  • Publication number: 20200027707
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: CHRISTOPHER HATEM, KEVIN ANGLIN
  • Publication number: 20190393019
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Patent number: 10411096
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 10, 2019
    Assignees: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC., VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Publication number: 20180248007
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Patent number: 9985101
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 29, 2018
    Assignees: Varian Semiconductor Equipment Associates, Inc., University of Florida Research Foundation, Inc.
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Publication number: 20170125526
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 4, 2017
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Patent number: 9553174
    Abstract: Embodiments of the present invention provide methods for forming fin structure with desired materials using a conversion process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming a fin structure on a substrate includes performing an directional plasma process on a fin structure formed from a substrate comprising a first type of atoms, the directional plasma process dopes a second type of atoms on sidewalls of the fin structure, performing a surface modification process to form a surface modified layer on the sidewalls of the fin structure reacting with the first type of atoms, replacing the first type of the atoms with the second type of the atoms in the fin structure during the surface modification process, and forming the fin structure including the second type of the atoms on the substrate.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ludovic Godet, Christopher Hatem, Matthew D. Scotney-Castle, Martin A. Hilkene
  • Patent number: 9520360
    Abstract: A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 13, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Christopher Hatem
  • Publication number: 20160326636
    Abstract: Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Inventors: Ludovic Godet, Christopher Hatem, Deepak Ramappa, Xianfeng Lu, Anthony Renau, Patrick Martin
  • Patent number: 9425027
    Abstract: Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 23, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Christopher Hatem, Deepak Ramappa, Xianfeng Lu, Anthony Renau, Patrick Martin
  • Publication number: 20160233162
    Abstract: A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Anthony Renau, Christopher Hatem
  • Patent number: 9337040
    Abstract: A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Christopher Hatem
  • Publication number: 20150279974
    Abstract: Embodiments of the present invention provide methods for forming fin structure with desired materials using a conversion process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming a fin structure on a substrate includes performing an directional plasma process on a fin structure formed from a substrate comprising a first type of atoms, the directional plasma process dopes a second type of atoms on sidewalls of the fin structure, performing a surface modification process to form a surface modified layer on the sidewalls of the fin structure reacting with the first type of atoms, replacing the first type of the atoms with the second type of the atoms in the fin structure during the surface modification process, and forming the fin structure including the second type of the atoms on the substrate.
    Type: Application
    Filed: February 13, 2015
    Publication date: October 1, 2015
    Inventors: Ludovic GODET, Christopher HATEM, Matthew D. SCOTNEY-CASTLE, Martin A. HILKENE
  • Publication number: 20140154834
    Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.
    Type: Application
    Filed: May 9, 2013
    Publication date: June 5, 2014
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Nicholas P.T. Bateman, Atul Gupta, Christopher Hatem, Deepak Ramappa
  • Patent number: 8697549
    Abstract: An improved method of creating thermoelectric materials which have high electrical conductivity and low thermal conductivity is disclosed. In one embodiment, the thermoelectric material is made by depositing a porous film onto a substrate, introducing a dopant into the porous film and annealing the porous film to activate the dopant. In other embodiments, additional amounts of dopant may be introduced via subsequent ion implantations of dopant into the deposited porous film.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 15, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Xianfeng Lu, Ludovic Godet, Christopher Hatem, John Hautala