Abstract: The present invention provides a data processing apparatus and method for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus comprises a data processing unit operable to execute instructions, with the data processing unit being responsive to a format conversion instruction to apply a format conversion operation to a number to perform a conversion between the fixed-point representation of the number and the floating-point representation of the number. Furthermore, a control field is provided which is arranged to provide a programmable value specifying a decimal point location within the fixed-point representation of the number, and the data processing unit is operable to reference the control field and to control the formal conversion operation in accordance with the programmable value.

Abstract: A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift indication based on a prediction of the number of bit positions by which the data value needs to be shifted in order to normalize the data value. Further, normalizer logic is used to apply a shift operation to the data value based on the shift indication. In addition, correction logic is operable in parallel with the normalizer logic to determine from the data value and a least significant bit of the shift indication whether the shift indication has correctly predicted the number of bit positions by which the data value needs to be shifted in order to normalize the data value, or whether instead the prediction is incorrect, and to generate an output signal dependent on that determination.

Abstract: A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic.

Abstract: The present invention provides a data processing apparatus and method for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi?1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: A data processing apparatus and method are provided for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m. The data processing apparatus comprises determination logic for determining the bit location of the most significant bit of the value expressed within the m-bit fixed point number, and low order bit analysis logic for determining from a selected number of least significant bits of the m-bit fixed point number a rounding signal indicating whether a rounding increment is required in order to generate the n-bit significand. Generation logic is then arranged in response to the rounding signal to generate a rounding bit sequence appropriate having regard to the bit location determined by the determination logic. Adder logic then adds the rounding bit sequence to the m-bit fixed point number to generate an intermediate result, whereafter normalisation logic shifts the intermediate result to generate the n-bit significand.

Abstract: A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand. First adder logic is then operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic.

Abstract: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and sum logic operable to perform a sum operation to add a first set of bits of each of the pair of 2n-bits vectors. Sticky determination logic is also provided for determining from a second set of bits of each of the pair of 2n-bit vectors a sticky value, and selector logic is then used to derive the n-bit result from the output of the sum logic with reference to the sticky value.

Abstract: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors, and half adder logic is used to produce from a plurality of most significant bits of the pair of 2n-bit vectors a corresponding plurality of carry and sum bits representing those plurality of most significant bits. Further, exponent determination logic determines a product exponent and also determines if that product exponent correspond to a predetermined exponent value.

Abstract: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is then arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation in order to generate a first rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition.

Abstract: The present invention provides a data processing apparatus and method for computing an absolute difference between portions of first and second data elements. The data processing apparatus comprises processing logic operable to perform a data processing operation on first and second data elements, the processing logic comprising comparison logic operable to compare at least a part of the first and second data elements in order to determine which of the first and second data elements is a larger data element. The comparison logic is operable to produce a comparison result which has a first value if the first data element is the larger data element and a second value if the second data element is the larger data element. The processing logic further comprises absolute difference logic operable to compute an absolute difference between a portion of the first data element and a portion of the second data element.

Abstract: The present invention provides a data processing apparatus and method for comparing first and second floating point operands to produce a comparison result. Each floating point operand has a sign component, an exponent component, and a fraction component. The data processing apparatus comprises first processing logic operable to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, the predetermined number being less than the total number of bits constituting the fraction component. The first processing logic is further operable to receive the sign components and the exponent components of the first and second floating point operands and to compare the sign components, the exponent components and the first components of the first and second floating point operands in order to produce a plurality of signals indicative of the comparison.

Abstract: The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists. Further, at least one detector logic unit is provided which is operable to receive both the first exponent and the second exponent and to detect the presence of the predetermined alignment condition.

Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components.