Patents by Inventor Christopher Ho

Christopher Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319144
    Abstract: A system for computational localization of fibrillation sources is provided. In some implementations, the system performs operations comprising generating a representation of electrical activation of a patient's heart and comparing, based on correlation, the generated representation against one or more stored representations of hearts to identify at least one matched representation of a heart. The operations can further comprise generating, based on the at least one matched representation, a computational model for the patient's heart, wherein the computational model includes an illustration of one or more fibrillation sources in the patient's heart. Additionally, the operations can comprise displaying, via a user interface, at least a portion of the computational model. Related systems, methods, and articles of manufacture are also described.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 11, 2019
    Assignee: The Regents of the University of California
    Inventors: David E. Krummen, Andrew D. McCulloch, Christopher Villongco, Gordon Ho
  • Publication number: 20190165146
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 30, 2019
    Inventors: Byron HO, Steven JALOVIAR, Jeffrey S. LEIB, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20190165147
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 30, 2019
    Inventors: Byron HO, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20190165145
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of one of the plurality of gate structures is removed to expose a portion of each of the plurality of fins. The exposed portion of each of the plurality of fins is removed. An insulating layer is formed in locations of the removed portion of each of the plurality of fins.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 30, 2019
    Inventors: Tahir GHANI, Byron HO, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20190164809
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 30, 2019
    Inventors: Heidi M. MEYER, Ahmet TURA, Byron HO, Subhash JOSHI, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20190164836
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 30, 2019
    Inventors: Tahir GHANI, Byron HO, Curtis W. WARD, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20190166056
    Abstract: Systems and methods of site traffic control are disclosed. In some example embodiments, a request for an online service to perform an operation is received from a user on a client device, and at least one overload condition for the online service is detected, or otherwise determined, with the overload condition(s) corresponding to a request time of the request. A standard of restriction is selected from a plurality of standards of restriction based on the overload condition(s), and the selected standard of restriction is used as a basis for either denying or permitting the user access to the operation of the online service.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 30, 2019
    Inventors: Yu Tang, Bryant Genepang Luk, Jennifer T. Robertson, Robert He, Christopher Diebold O'Toole, Jason Ziaja, Ananya Das, Jun Ho Cho, Zi Won Ahn
  • Publication number: 20190164961
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
    Type: Application
    Filed: December 30, 2017
    Publication date: May 30, 2019
    Inventors: Byron HO, Chun-Kuo HUANG, Erica THOMPSON, Jeanne LUCE, Michael L. HATTENDORF, Christopher P. AUTH, Ebony L. MAYS
  • Publication number: 20190165131
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Application
    Filed: December 30, 2017
    Publication date: May 30, 2019
    Inventors: Tahir GHANI, Byron HO, Michael L. HATTENDORF, Christopher P. AUTH
  • Patent number: 10304940
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Publication number: 20190151074
    Abstract: A composite hollow lumen and a method for producing the lumen are provided. The lumen includes a tubular textile formed of yarns having a first tensile strength and a matrix material in which the tubular textile is embedded to form a conduit having a bore and a sidewall substantially impermeable to liquid. The matrix material has a second tensile strength that is lower than the first tensile strength. The method for producing a composite lumen includes selecting yarns having a first tensile strength, selecting an elastomeric matrix material having a second tensile strength that is lower that the first tensile strength, forming a tubular textile of the yarns, and embedding the tubular textile in the matrix material to form a conduit having a bore and conduit walls that are substantially impermeable to liquid. The elastomeric matrix material is a biodegradable or bioresorbable polyester.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventors: Peter D. GABRIELE, Sean Christopher GASBY, Jeremy J. HARRIS, Alicia RUTHRAUFF, Swati AMIN, Seth A. WINNER, Ryan HENIFORD, Richard BALTHASER, Emily Y. HO
  • Patent number: 10294185
    Abstract: An improved process for the manufacture of technical grade (meth)acrylic acid, e.g., acrylic acid, the process comprising producing a hydrated reaction product from the gas-phase oxidation of at least one (meth)acrylic acid precursor, e.g., propylene, followed by first dehydrating and then concentrating the reaction product, the improvement comprising controlling at least one of the water, acetic acid and (meth)acrylic acid content of the reaction product during the purification of the reaction product using on-line, near IR spectroscopy.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Arkema Inc.
    Inventors: Timothy D. Ligon, Olan S. Fruchey, Christopher T. Reeves, Fungau Ho, Roger L. Roundy, William G. Etzkorn, Mahmood N. A. Jawaid, Patrick M. Wiegand
  • Patent number: 10255650
    Abstract: A system has a central processing unit (CPU) and a graphics processing unit (GPU) that includes one or more registers. The GPU can change a resource descriptor in one of the GPU's registers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 9, 2019
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventors: Richard B. Stenson, Steven Osman, Jun Murakawa, Christopher Ho
  • Publication number: 20180365034
    Abstract: In an example method, a request for a dynamic access link is received from a first device. The request includes data identifying a first network resource. A subject associated with the first network resource is identified, and one or more additional network resources pertaining to the subject are determined. The dynamic access link is determined, and the dynamic access link is provided to the first device. A network resource access request is received from a second device. The network resource access request is generated responsive to the dynamic access link being selected. Responsive to receiving the network resource access request, at least one of the first resource or the one or more additional network resources is chosen, and a network address of the chosen resource is provided to the second device.
    Type: Application
    Filed: January 25, 2018
    Publication date: December 20, 2018
    Inventors: Paul Norman Becotte, IV, Christopher Ho Sang, Shirley Chen
  • Publication number: 20180240272
    Abstract: Systems, methods, and devices are disclosed for rendering computer graphics. In various embodiments, a displacement map is created for a plurality of surfaces and a tessellation process is initiated. It is determined that the tessellation density of a first set of surfaces and a second set of surfaces should be modified based on the displacement map. Based on the displacement map, a tessellation factor scale for each surface of the first set of surfaces is increased and a tessellation factor scale for each surface of the second set of surfaces is decreased, respectively.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 23, 2018
    Inventors: John Doolittle, Jun Murakawa, Christopher Ho
  • Patent number: 9495722
    Abstract: A method for processing graphics for a GPU program, translating instructions from a shading language into an intermediate language with a front end of a GPU compiler; translating the instructions from the intermediate language into a GPU object language with a back end of the GPU compiler; wherein the instructions in the shading language include instructions defining a layout of resources for the GPU program.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: November 15, 2016
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventors: Richard B. Stenson, Christopher Ho, Mark E. Cerny, Steven Osman, Jun Murakawa, Dmitri Shtilman, Jason Scanlin
  • Patent number: D764579
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 23, 2016
    Assignee: Myriad Genetics, Inc.
    Inventors: Cindy H. Solomon, Karla R. Bowles, Brian A. Allen, Eric T. Rosenthal, Christopher Ho, Kirsten H. Trahan, Thomas M. Collins, Devin Howells
  • Patent number: D764580
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 23, 2016
    Assignee: Myriad Genetics, Inc.
    Inventors: Cindy H. Solomon, Karla R. Bowles, Brian A. Allen, Eric T. Rosenthal, Christopher Ho, Kirsten H. Trahan, Thomas M. Collins, Devin Howells
  • Patent number: D764581
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 23, 2016
    Assignee: Myriad Genetics, Inc.
    Inventors: Cindy H. Solomon, Karla R. Bowles, Brian A. Allen, Eric T. Rosenthal, Christopher Ho, Kirsten H. Trahan, Thomas M. Collins, Devin Howells
  • Patent number: D849401
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 28, 2019
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Daniel J. Coster, Daniele De Iuliis, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Christopher J. Stringer, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer