Patents by Inventor Christopher J. Abel
Christopher J. Abel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8861580Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.Type: GrantFiled: May 16, 2006Date of Patent: October 14, 2014Assignee: Agere Systems LLCInventors: Christopher J. Abel, Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith
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Patent number: 8514920Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: GrantFiled: July 26, 2012Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 8483266Abstract: Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.Type: GrantFiled: July 30, 2010Date of Patent: July 9, 2013Assignee: LSI CorporationInventors: Christopher J. Abel, Lane A. Smith, Philip N. Jenkins, Brett D. Hardy, Vladimir Sindalovsky
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Publication number: 20120287983Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: ApplicationFiled: July 26, 2012Publication date: November 15, 2012Applicant: LSI CORPORATIONInventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 8275025Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: GrantFiled: February 27, 2009Date of Patent: September 25, 2012Assignee: LSI CorporationInventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 8165253Abstract: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.Type: GrantFiled: August 28, 2008Date of Patent: April 24, 2012Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Vladimir Sindalovsky, Lane A. Smith
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Publication number: 20100220776Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Inventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
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Patent number: 7777538Abstract: Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.Type: GrantFiled: March 3, 2006Date of Patent: August 17, 2010Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Weiwei Mao
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Patent number: 7714667Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.Type: GrantFiled: November 2, 2007Date of Patent: May 11, 2010Assignee: Agere Systems Inc.Inventors: Xingdong Dai, Yasser Ahmed, Christopher J. Abel, Shawn Michael Logan
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Publication number: 20100054386Abstract: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Inventors: Christopher J. Abel, Vladimir Sindalovsky, Lane A. Smith
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Patent number: 7656255Abstract: Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.Type: GrantFiled: February 28, 2007Date of Patent: February 2, 2010Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Robert J. Kapuschinsky, Gary D. Polhemus
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Patent number: 7649933Abstract: Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.Type: GrantFiled: April 28, 2006Date of Patent: January 19, 2010Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Mohammad S. Mobin, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith
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Publication number: 20090115536Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.Type: ApplicationFiled: November 2, 2007Publication date: May 7, 2009Applicant: AGERE SYSTEMS INC.Inventors: Xingdong Dai, Yasser Ahmed, Christopher J. Abel, Shawn Michael Logan
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Patent number: 7496780Abstract: Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.Type: GrantFiled: February 11, 2003Date of Patent: February 24, 2009Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Joseph Anidjar, Abhishek Duggal, Donald R. Laturell
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Patent number: 7425856Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.Type: GrantFiled: June 30, 2006Date of Patent: September 16, 2008Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Joseph Anidjar, Vladimir Sindalovsky, Craig B. Ziemer
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Publication number: 20080204171Abstract: Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Inventors: Christopher J. Abel, Robert J. Kapuschinsky, Gary D. Polhemus
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Patent number: 7366086Abstract: A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.Type: GrantFiled: February 18, 2004Date of Patent: April 29, 2008Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Joseph Anidjar, James D. Chlipala, Abhishek Duggal, Donald R. Laturell
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Patent number: 7352313Abstract: Methods and apparatus are provided for improved digital-to-analog conversion. The disclosed digital-to-analog converter comprises a master digital-to-analog converter that generates a master analog value, and a slave digital-to-analog converter that generates a slave analog value that is based on the master analog value. The slave analog value can be, for example, substantially proportional to the master analog value. The master D/A converter can be varied during a coarse tuning mode, while the input to the slave D/A can be fixed, for example, to an approximately mid-range value until the master analog value satisfies one or more predefined conditions. Thereafter, during a fine tuning mode, the slave D/A converter can be varied, while the master D/A converter is fixed, so that the output Y is equal to a desired value (within a specified tolerance).Type: GrantFiled: May 31, 2005Date of Patent: April 1, 2008Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Peter C. Metz
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Patent number: 7330060Abstract: Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.Type: GrantFiled: September 7, 2005Date of Patent: February 12, 2008Assignee: Agere Systems Inc.Inventors: Christopher J. Abel, Abhishek Duggal, Peter C. Metz, Vladimir Sindalovsky
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Publication number: 20080001644Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Christopher J. Abel, Joseph Anidjar, Vladimir Sindalovsky, Craig B. Ziemer