Abstract: A multi-interface memory can include a memory package that includes a memory device and host interfaces coupled to the memory device. Each of the host interfaces is configured to operate according to a different protocol. The memory package can be coupled to a host via one or more of the host interfaces. More than one of the host interfaces can share a contact.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cells or retires memory cells based on the provided ECC data.

Abstract: Respective values of a subset of the plurality of memory cells of a memory device are compared to a pattern of pre-programmed memory cells. The pattern pre-programmed memory cells comprise representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied. Responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, a temperature reading from a thermal sensor coupled to the memory device is identified. Responsive to determining that the temperature reading does not correspond to a temperature criterion, determining that the thermal sensor has failed.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.

Abstract: A method comprising receiving, at a memory sub-system from a host system, receiving, at one or more configuration parameters reflecting an expected type of use of the memory sub-system; receiving one or more environmental parameters of the memory sub-system, wherein the environmental parameters reflect characteristics of an environment of the memory sub-system; and selecting a programming operation parameter to be utilized by the memory sub-system based on the configuration parameters and environmental parameters.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cellsor retires memory cells based on the provided ECC data.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: Disclosed is a system, and a method of using the system, that includes a memory component and a processing device. The processing device provides, to a host system, a failure notification that includes an indication of memory cell(s) of the memory device storing a data that was corrupted during a memory operation. The processing device then receives a replacement data from the host system. The replacement data is provided in response to the host system identifying a range of logical addresses corresponding to the corrupted data, based on geometric parameters of the memory device and the failure notification.

Abstract: A vehicle-based apparatus for noise injection and monitoring includes a first processing device coupled to a plurality of components and a second processing device coupled to the plurality of components. The second processing device injects noise into at least one component among the plurality of components and monitors behavior of the at least one component in response to the injected noise. The second processing device determines, based, at least in part, on the monitored behavior of the at least one component responsive to the injected noise, a susceptibility to the injected noise exhibited by the at least one component and transmits signaling indicative of the determined susceptibility to the injected noise exhibited by the at least one component to the first processing device.

Abstract: A vehicle-based safety processor apparatus includes a first processing device coupled to a plurality of components and a second processing device coupled to the plurality of components. The second processing device can monitor characteristics of the plurality of components and determine a threat level of at least one component of the plurality of components based on at least one the characteristics. The second processing device can further determine whether the threat level meets or exceeds a threshold threat level for the at least one component and transmit signaling indicative of the determination that the threat level meets or exceeds the threshold threat level for the at least one component to the first processing device responsive to the determination that the threat level meets or exceeds the threshold threat level for the at least one component.

Abstract: A host system can be queried to determine whether new data has been received based on a first time interval. After completion of the first time interval, a determination can be made as to whether the new data has been received and whether a portion of the new data was not stored. In response to the portion of the new data not being stored, the host system can be queried to determine whether subsequent data has been received based on a second time interval where the second time interval is different from first time interval.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: A temperature reading from a thermal sensor connected to a memory device is determined. The memory device comprises a plurality of memory cells. At least one of a logical capacity criterion or a physical capacity criterion is determined based on the temperature reading from the thermal sensor. Responsive to determining that at least one of the logical capacity of a first data block of the plurality of memory cells configured as a first memory type satisfies the logical capacity criterion or a physical capacity of the first data block of the plurality of memory cells configured as the first memory type satisfies the physical capacity criterion, data from the first data block is migrated to a second data block of the plurality of memory cells configured as a second memory type.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: Respective values of a subset of the plurality of memory cells of a memory device are compared to a pattern of pre-programmed memory cells. The pattern pre-programmed memory cells comprise representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied. Responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, a temperature reading from a thermal sensor coupled to the memory device is identified. Responsive to determining that the temperature reading does not correspond to a temperature criterion, determining that the thermal sensor has failed.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A program operation on a subset of a plurality of memory cells is performed. A sense operation on the subset of the plurality of memory cells is performed to determine respective values stored in the subset of the plurality of memory cells. One or more patterns of pre-programmed memory cells of the memory device are identified. The one or more patterns comprise representations of values of the pre-programmed memory cells when at least one of a first temperature criterion or a second temperature criterion is satisfied. The respective values of the subset of the plurality of memory cells are compared to the values of the pre-programmed memory cells in the one or more patterns. Based on the comparison, a reading from a thermal sensor coupled to the memory device is determined to satisfy an accuracy criterion.