Abstract: Examples may forward an input/output (IO) request with use of kernel-level instructions. Examples may receive the IO request via a port of a standby controller, generate an alternate version of the IO request using at least kernel-level instructions of the standby controller, and provide the alternate version of the IO request to physical memory of the active controller by providing the alternate version of the IO request to a designated region of physical memory of the standby controller that is mapped to a designated region of the physical memory of the active controller.

Abstract: A system may include a persistent storage device, a low latency cache device, a volatile memory; and a processor. The processor is to store a data structure in the volatile memory that is usable to directly translate a block logical address for targeted data to a candidate physical location on the cache device, store a multilevel translation index in the volatile memory for translating the block logical address for the targeted data to an expected physical location of the targeted data on the cache device and attempt accessing the targeted data at the candidate physical location retrieved from the direct cache address translation data structure. In response to the targeted data not being at the candidate physical address, access the targeted data at the expected physical location retrieved from the multilevel translation index.

Abstract: Examples may forward an input/output (IO) request with use of kernel-level instructions. Examples may receive the IO request via a port of a standby controller, generate an alternate version of the IO request using at least kernel-level instructions of the standby controller, and provide the alternate version of the IO request to physical memory of the active controller by providing the alternate version of the IO request to a designated region of physical memory of the standby controller that is mapped to a designated region of the physical memory of the active controller.

Abstract: Examples may forward an input/output (IO) request with use of kernel-level instructions. Examples may receive the IO request via a port of a standby controller, generate an alternate version of the IO request using at least kernel-level instructions of the standby controller, and provide the alternate version of the IO request to physical memory of the active controller by providing the alternate version of the IO request to a designated region of physical memory of the standby controller that is mapped to a designated region of the physical memory of the active controller.

Abstract: A system may include a persistent storage device, a low latency cache device, a volatile memory; and a processor. The processor is to store a data structure in the volatile memory that is usable to directly translate a block logical address for targeted data to a candidate physical location on the cache device, store a multilevel translation index in the volatile memory for translating the block logical address for the targeted data to an expected physical location of the targeted data on the cache device and attempt accessing the targeted data at the candidate physical location retrieved from the direct cache address translation data structure. In response to the targeted data not being at the candidate physical address, access the targeted data at the expected physical location retrieved from the multilevel translation index.

Abstract: Examples may forward an input/output (IO) request with use of kernel-level instructions. Examples may receive the IO request via a port of a standby controller, generate an alternate version of the IO request using at least kernel-level instructions of the standby controller, and provide the alternate version of the IO request to physical memory of the active controller by providing the alternate version of the IO request to a designated region of physical memory of the standby controller that is mapped to a designated region of the physical memory of the active controller.

Abstract: A system may include a persistent storage device, a low latency cache device, a volatile memory; and a processor. The processor is to store a data structure in the volatile memory that is usable to directly translate a block logical address for targeted data to a candidate physical location on the cache device, store a multilevel translation index in the volatile memory for translating the block logical address for the targeted data to an expected physical location of the targeted data on the cache device and attempt accessing the targeted data at the candidate physical location retrieved from the direct cache address translation data structure. In response to the targeted data not being at the candidate physical address, access the targeted data at the expected physical location retrieved from the multilevel translation index.

Abstract: This disclosure is directed to a technique for memory management where physical memory areas may be partitions into a hierarchy of portions, the hierarchy may include a domain level that includes a page level that includes a slice level that includes an object level. Objects within a slice are a consistent size but may be different sized for different slices. A set of states reflecting memory usage status for each of the slices includes: a clean state for unused; a partial state; a full state; and a dirty state. Responses to allocation requests may be performed by selecting objects that are in a most preferred state based on a state allocation cost and a memory allocation cost either alone or in combination. A compact memory layout may be used to reduce run-time fragmentation of memory.

Abstract: This disclosure is directed to a technique for memory management where physical memory areas may be partitions into a hierarchy of portions, the hierarchy may include a domain level that includes a page level that includes a slice level that includes an object level. Objects within a slice are a consistent size but may be different sized for different slices. A set of states reflecting memory usage status for each of the slices includes: a clean state for unused; a partial state; a full state; and a dirty state. Responses to allocation requests may be performed by selecting objects that are in a most preferred state based on a state allocation cost and a memory allocation cost either alone or in combination. A compact memory layout may be used to reduce run-time fragmentation of memory.