Abstract: A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC type processor machine instructions residing in memory. The invention implements the same algorithm represented by the sequence of encoded instructions, but executes the algorithm consuming significantly fewer clock cycles than would be consumed by the processor originally targeted to execute the sequence of encoded instructions.

Abstract: A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC type processor machine instructions residing in memory. The invention implements the same algorithm represented by the sequence of encoded instructions, but executes the algorithm consuming significantly fewer clock cycles than would be consumed by the processor originally targeted to execute the sequence of encoded instructions.

Abstract: A pulse rephasing circuit and method for receiving an input signal and generating an output signal includes a circuit for generating a control voltage of magnitude related to a phase difference between the input and output signals. The circuit for generating a control voltage may be, for example, a multiplier circuit to which both the input and output signals are applied. A delay circuit receives the input signal to produce an output signal that has been delayed with respect to the input signal an amount related to the magnitude of the control voltage. The delay circuit may include a capacitor, a circuit for linearly charging the capacitor, a circuit for comparing the control voltage to a voltage charged on the capacitor, and a circuit for generating a state change in the output signal when the voltage charged on the capacitor exceeds the control voltage.

Abstract: An improved auto-zeroing circuit for reducing offset currents from high impedance CMOS current drivers. The Auto zero circuit of the present invention contains means to disconnect the output of the current driver from its low impedance load, means to substantially simultaneously connect a capacitor to the output of the current driver, and means to use the output voltage of the current sources during the zeroing mode to adjust the voltage on the capacitor. The capacitor voltage is then used to adjust either of the two output current sources to reduce the offset currents.

Abstract: A method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements. The present invention uses an auto-centering, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of a CMOS current driver using cascoded or resistor source de-generated FET devices.