Abstract: A multiposition switch is connected to two input data buses which buses can apply binary digital signals of two operands to the switch at one time. An output data bus is also connected to the switch. Depending upon the position of the switch, bits from one or both of the operands as well as bits from other sources are applied by the switch to the output bus so that the format of the operand on the output bus has a predetermined relationship to the operands on the input buses.

Abstract: A method of and apparatus for simultaneously enabling different parts of an input television signal to be made available is used as a television standards converter. Successive lines of an input television signal are cyclically written into n (eg 4) sucessive random access store sections, using in each cycle the same addresses for the different sections. The write addresses are incremented for sucessive cycles. The sections are read from using for each section addresses which are related to each other and to the write addresses so as to access a desired set of up to n sucessive lines. These lines are combined by weighted addition to provide an interpolated output line. The read addresses are derived by counting the desired output lines during each field and multiplying the count by the line conversion ratio. The integral part of the resultant controls the read addresses and the non-integral part controls the weighted addition. A total storage of two fields is used, each divided into sections.

Abstract: A method of and apparatus for simultaneously enabling different parts of an input television signal to be made available is used as a television standards converter. Successive lines of an input television signal are cyclically written into n (eg 4) successive random access store sections, using in each cycle the same addresses for the different sections. The write addresses are incremented for successive cycles. The sections are read from using for each section addresses which are related to each other and to the write addresses so as to access a desired set of up to n successive lines. These lines are combined by weighted addition to provide an interpolated output line. The read addresses are derived by counting the desired output lines during each field and multiplying the count by the line conversion ratio. The integral part of the resultant controls the read addresses and the non-integral part controls the weighted addition. A total storage of two fields is used, each divided into sections.