Abstract: A synthetic impedance telecommunication line driver has no electrical energy-dissipating elements in series with its output, and synthesizes its output impedance in accordance with current fed back from an output current (mirror) sensing circuit. This allows the driver to realize substantially reduced power requirements for driving a telecommunication line, such as, but not limited to a DSX-1 line. The driver includes an operational amplifier having a first polarity input coupled through an input resistor to an input port, to which a signal voltage to applied to an output port is coupled. A second polarity input of the amplifier is coupled to a reference voltage. A feedback resistor is coupled between the amplifier output and its inverting input. An output current-dependent current source, such as a current mirror coupled in circuit with the output node, generates a current as a small fraction k of the output current.

Abstract: A synthetic impedance telecommunication line driver has no electrical energy-dissipating elements in series with its output, and synthesizes its output impedance in accordance with current fed back from an output current (mirror) sensing circuit. This allows the driver to realize substantially reduced power requirements for driving a telecommunication line, such as, but not limited to a DSX-1 line. The driver includes an operational amplifier having a first polarity input coupled through an input resistor to an input port, to which a signal voltage to applied to an output port is coupled. A second polarity input of the amplifier is coupled to a reference voltage. A feedback resistor is coupled between the amplifier output and its inverting input. An output current-dependent current source, such as a current mirror coupled in circuit with the output node, generates a current as a small fraction k of the output current.

Abstract: A circuit arrangement for controlling the read-out of stored information composed of first and second random access memories each having a plurality of addressable memory locations having a preferred order of write-in, an address input, an information input, and an information output, a first signal source connected to the information input of the second memory for writing information values into the memory locations of the second memory in the preferred write-in order, a second signal source connected to the information input of the first memory for writing into the memory locations of the first memory signals representing respective addresses of the second memory, and signal conducting device connected between the information output of the first memory and the address input of the second memory for delivering address signals to the second memory derived from values stored in successive memory locations of the first memory.