Abstract: A circuit arrangement for controlling the read-out of stored information composed of first and second random access memories each having a plurality of addressable memory locations having a preferred order of write-in, an address input, an information input, and an information output, a first signal source connected to the information input of the second memory for writing information values into the memory locations of the second memory in the preferred write-in order, a second signal source connected to the information input of the first memory for writing into the memory locations of the first memory signals representing respective addresses of the second memory, and signal conducting device connected between the information output of the first memory and the address input of the second memory for delivering address signals to the second memory derived from values stored in successive memory locations of the first memory.