Patents by Inventor Christopher J. Gonzalez
Christopher J. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090604Abstract: Various aspects disclosed relate to structure such as a textile, a garment, a garment component, footwear, or a footwear component. The present disclosure includes the structure having a first region having one of more first fibers. An individual first fiber includes co-extruded first and second filaments, the first filament formed of a first thermoplastic polymeric material. Due to expansion or contraction of the one or more first fibers, the first region contracts or expands on a change in relative humidity, relative to an equilibrium state of the first region prior to the change in relative humidity.Type: ApplicationFiled: October 4, 2023Publication date: March 21, 2024Inventors: Eduardo Alberto Gonzalez de los Santo, David M. Litton, Romesh Patel, Christopher J. Ranalli, Joshua Patrick Williams
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Patent number: 11175925Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.Type: GrantFiled: November 29, 2017Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 11175924Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.Type: GrantFiled: October 6, 2017Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108033Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.Type: ApplicationFiled: November 29, 2017Publication date: April 11, 2019Inventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Publication number: 20190108032Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
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Patent number: 8458501Abstract: A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.Type: GrantFiled: July 27, 2010Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Christopher J. Gonzalez, Moinuddin K. Qureshi, Victor Zyuban
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Publication number: 20120030481Abstract: A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.Type: ApplicationFiled: July 27, 2010Publication date: February 2, 2012Applicant: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Christopher J. Gonzalez, Moinuddin K. Qureshi, Victor Zyuban
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Patent number: 7836418Abstract: The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.Type: GrantFiled: March 24, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: William A. Binder, Christopher J. Gonzalez, Paul D. Kartschoke, Sherwin C. Murphy, Jr.
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Patent number: 7715222Abstract: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: GrantFiled: September 15, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Patent number: 7602635Abstract: A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: GrantFiled: November 29, 2007Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Publication number: 20090241079Abstract: The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William A. BINDER, Christopher J. GONZALEZ, Paul D. KARTSCHOKE, Sherwin C. MURPHY, JR.
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Publication number: 20090141536Abstract: A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices
Publication number: 20090144677Abstract: A design structure for a circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The design structure for the circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer -
Patent number: 7490308Abstract: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.Type: GrantFiled: March 31, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Michael S. Gray, Matthew T. Guzowski, Jason D. Hibbeler, Stephen I. Runyon, Xiaoyun K. Wu
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Patent number: 7480810Abstract: Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop.Type: GrantFiled: February 14, 2006Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Paul D. Kartschoke, Vinod Ramadurai, Mathew I. Ringler
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Publication number: 20090010043Abstract: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: ApplicationFiled: September 15, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Patent number: 7450413Abstract: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: GrantFiled: August 11, 2006Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Patent number: 7352252Abstract: A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.Type: GrantFiled: July 11, 2006Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Publication number: 20080037313Abstract: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.Type: ApplicationFiled: August 11, 2006Publication date: February 14, 2008Inventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer
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Publication number: 20080024232Abstract: A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.Type: ApplicationFiled: July 11, 2006Publication date: January 31, 2008Inventors: Christopher J. Gonzalez, Vinod Ramadurai, Norman J. Rohrer