Abstract: The present disclosure generally relates to displaying information related to a physical activity. In some embodiments, methods and user interfaces for managing the display of information related to a physical activity are described.

Abstract: Systems and methods are disclosed that provide smart alerts to users, e.g., alerts to users about diabetic states that are only provided when it makes sense to do so, e.g., when the system can predict or estimate that the user is not already cognitively aware of their current condition, e.g., particularly where the current condition is a diabetic state warranting attention. In this way, the alert or alarm is personalized and made particularly effective for that user. Such systems and methods still alert the user when action is necessary, e.g., a bolus or temporary basal rate change, or provide a response to a missed bolus or a need for correction, but do not alert when action is unnecessary, e.g., if the user is already estimated or predicted to be cognitively aware of the diabetic state warranting attention, or if corrective action was already taken.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A system and method for preventing untrusted nodes from sending or receiving management communications. In an environment such as an InfiniBand communication fabric, a management packet (e.g., a packet traversing virtual lane 15) is one of four types: 1) Request from a manager node (e.g., Subnet Manager or SM) to an endnode; 2) Reply from an endnode to a request from the manager; 3) Request from an endnode to the manager; and 4) Reply from the manager to the endnode. Switches (and other routing devices) are configured to allow untrusted nodes to send management packets of types 2 and 3 only, and to receive management packets of types 1 and 4 only. Trusted nodes (e.g., manager nodes, switches) can send and receive all types. Each port of a switch or routing device has an associated indicator reflecting the level of trust afforded the node or switch coupled to the port.

Abstract: A communications node connected to a packet-switched data input/output network, such as an InfiniBand® network, has a plurality of processing cores on which a subnet management agent may be run. The subnet management agent processes management instructions relating to node configuration. In the invention, the processing core running the subnet management agent may be dynamically changed by one or more of the processing cores in the node. The processing cores may include a host processor, a service processor and an embedded processor, dedicated to a host channel adapter, which provides a communications interface between the network and the node. Various methods may be used to move the subnet management agent, including the use of a register to which one or more of the processing cores may write, and in which is stored an indication of which processing core is currently running the subnet management agent.

Abstract: An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

Abstract: A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a memory window for direct memory access. The method includes communicating a selected data-integrity-checking scheme from a specified set of schemes to another processor to off-load calculation of the data-integrity-checking value. A related method associates a message to be received with a data-integrity-checking scheme, so that a receiving processor can calculate the data-integrity-checking value and transmit both the value and the message to another processor.

Abstract: A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.

Abstract: A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a transaction stream. The transaction stream, including the annotations, are subsequently observed by a trace unit for debug or other analysis. In one embodiment, a processing unit includes a trace address register and an annotation enable bit. The trace address register is configured to store an address corresponding to a trace unit and the enable bit is configured to indicate whether annotation transactions are to be generated. Annotation instructions are added to operating system or user code at locations where annotations are desired. In one embodiment, annotation transactions correspond to transaction types which are not unique to annotation transactions. In one embodiment, an annotation instruction includes a reference to the trace address register which contains the address of the trace unit.

Abstract: A system for permitting remote user access to regions of memory that have been exported for remote direct memory access purposes. The system supports dynamically changing access privileges to remote users without requiring intervention from an operating system. The system may include a memory region table and a memory window table for supporting address translations. Entries in the memory window table may include a region remote access key and a window remote access key. The memory region table may include fields for a physical address, an access value, a protection domain value, and a length of memory region.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Abstract: A communications node connected to a packet-switched data input/output network, such as an InfiniBand® network, has a plurality of processing cores on which a subnet management agent may be run. The subnet management agent processes management instructions relating to node configuration. In the invention, the processing core running the subnet management agent may be dynamically changed by one or more of the processing cores in the node. The processing cores may include a host processor, a service processor and an embedded processor, dedicated to a host channel adapter, which provides a communications interface between the network and the node. Various methods may be used to move the subnet management agent, including the use of a register to which one or more of the processing cores may write, and in which is stored an indication of which processing core is currently running the subnet management agent.

Abstract: A system and method for performing a sync operation for multiple devices in a computer system is provided. The computer system may include a plurality of devices and a plurality of agents. The agents may be configured to perform tasks on behalf of the devices. A busy bit and a counter may be included for each of the agents. One of the devices may become an observer by initiating a sync operation. In response to a sync operation, busy agents may be identified using the busy bit for each agent. The busy agents may then be monitored to determine when each one has cycled using the busy bit and the counter for each busy agent. A busy agent may be determined to have cycled in response to its busy bit indicating that it is no longer busy or in response to its counter value differing from the counter value at the time the sync operation was initiated. Once each of the busy agents have cycled, the observer may determine that the sync operation is complete.

Abstract: A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a memory window for direct memory access. The method includes communicating a selected data-integrity-checking scheme from a specified set of schemes to another processor to off-load calculation of the data-integrity-checking value. A related method associates a message to be received with a data-integrity-checking scheme, so that a receiving processor can calculate the data-integrity-checking value and transmit both the value and the message to another processor.

Abstract: A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.

Abstract: A system for permitting remote user access to regions of memory that have been exported for remote direct memory access purposes is provided. The system supports dynamically changing access privileges to remote users without requiring intervention from an operating system.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Abstract: A multiprocessing computer system includes a plurality of processing nodes, each having one or more processors, a memory, and a system interface. The plurality of processing nodes may be interconnected through a global interconnect network which supports cluster communications. The system interface of an initiating node may launch a request to a remote node's memory or I/O. The computer system implements an error communication reporting mechanism wherein errors associated with remote transactions may be reported back to a particular processor which initiated the transaction. Each processor includes an error status register that is large enough to hold a transaction error code. The protocol associated with a local bus of each node (i.e., a bus interconnecting the processors of a node to the node's system interface) includes acknowledgement messages for transactions when they have completed.

Abstract: A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a transaction stream. The transaction stream, including the annotations, are subsequently observed by a trace unit for debug or other analysis. In one embodiment, a processing unit includes a trace address register and an annotation enable bit. The trace address register is configured to store an address corresponding to a trace unit and the enable bit is configured to indicate whether annotation transactions are to be generated. Annotation instructions are added to operating system or user code at locations where annotations are desired. In one embodiment, annotation transactions correspond to transaction types which are not unique to annotation transactions. In one embodiment, an annotation instruction includes a reference to the trace address register which contains the address of the trace unit.