Abstract: A hierarchy of schedules propagate minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.) of scheduled items can be propagated through the hierarchy of schedules accordingly without being blocked behind a lower priority or different type of traffic.

Abstract: Schedules may use burst tolerance values to adjust the scheduling in a time-based schedule, such as, but not limited to, adjusting for accumulated but not used bandwidth, and/or adjusting eligibility of schedule entries. A best schedule item associated with an eligible schedule entry of a schedule is identified. Whether or not a particular schedule entry is eligible is typically determined based on the relationship of an associated timestamp with a current scheduling time, such as its timestamp being less than or equal to the current time. A burst tolerance time bound might also be used to allow certain priorities and/or types of items to be considered eligible if even its timestamp exceeds the current time by an amount, but less than or equal to the burst tolerance time bound.

Abstract: Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.

Abstract: Eligible entries are scheduled using an approximated finish delay identified for an entry based on an associated speed group. One implementation maintains schedule entries, each respectively associated with a start time and a speed group. Each speed group is associated with an approximated finish delay. An approximated earliest finishing entry from the eligible schedule entries is determined that has an earliest approximated finish time, with the approximated finish time of an entry being determined based on the entry's start time and the approximated finish delay of the associated speed group. The scheduled action corresponding to the approximated earliest finishing entry is then typically performed. The action performed may, for example, correspond to the forwarding of one or more packets, an amount of processing associated with a process or thread, or any activity associated with an item.

Abstract: A hierarchy of schedules propagate minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.) of scheduled items can be propagated through the hierarchy of schedules accordingly without being blocked behind a lower priority or different type of traffic.

Abstract: Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.

Abstract: Rate computations are performed such as for use in scheduling activities, such as, but not limited to packets, processes, traffic flow, etc. One implementation identifies an approximated inverse rate, a fix-up adjustment value, and a quantum. An activity measurement value is maintained based on a measure of activity, and a rate control value is maintained based on the measure of activity and the approximated inverse rate. The fix-up adjustment value is applied once each quantum to the rate control value to maintain rate accuracy of the activity. In one implementation, the control value is a scheduling value used for determining when to perform a next part of the activity (e.g., send one or more packets). Scheduling rates are efficiently and compactly stored in an inverse form, which may have advantages in terms of rate granularity, accuracy, and the ability to deliver service smoothly.

Abstract: A data communications device interconnected for channelized communication overcomes the problems associated with message traffic starvation on outgoing traffic channels by forming arbitration, or speed groups of logical interfaces and allocating scheduling resources in proportion to the bandwidth attributed to each group relative to the total bandwidth of the device. Incoming messages have a transmission rate based on QOS, content type, or other constraints. A categorizer determines arbitration groups of the outgoing messages based on the transmission rate of the message. The scheduler allocates dequeue requests among the groups according to the proportion allocated to the arbitration group. A dequeue manager drains the outgoing messages from the arbitration groups at a rate in proportion to the total percentage of outgoing transmission bandwidth represented by the group by selecting a message from among the arbitration groups according to the computed proportion.

Abstract: Queues are scheduled for outputting data using a hierarchical tree. Each level of the hierarchical tree includes multiple entries for storing status information associated with the queues. For example, a given entry of the tree stores multi-parameter status information associated with a corresponding queue to be serviced. To determine which of the queues is next in line for servicing, a logic circuit compares the multi-parameter status information stored in two or more entries of the tree. The next scheduled queue or highest priority queue in the tree is then serviced by outputting at least some of its data.

Abstract: A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specific queue scheduling requirements for the computerized device. The computerized device extracts a first time stamp value and a second time stamp value associated with a first queue and a second queue, respectively. The computerized device receives instructions to configure a table of the GSP with scheduling entries. The computerized device compares the first time stamp value with the second time stamp value to form a comparison result. The computerized device then selects a decision instruction from the table, based upon the comparison result, and identifies a preferred queue of the first queue and the second queue, based upon the decision instruction.

Abstract: Conventional schedulers employ designs allocating specific processor and memory resources, such as memory for configuration data, state data, and scheduling engine processor resources for specific aspects of the scheduler, such as layers of the scheduling hierarchy, each of which consumes dedicated processor and memory resources. A generic, iterative scheduling engine, applicable to an arbitrary scheduling hierarchy structure having a variable number of hierarchy layers, receives a scheduling hierarchy structure having a predetermined number of layers, and allocates scheduling resources such as instructions and memory, according to scheduling logic, in response to design constraints and processing considerations.

Abstract: Conventional schedulers propagate entries by either polling until an entry is ready, or alternatively, by attaching a so-called “readiness time” to entries. A scheduler which recognizes the readiness time avoids consuming a parent schedule with polling, or with burdening entries with a future readiness time. The system of the present invention employs a deferral queue for deferring entries in response to pop requests from a parent schedule. The child schedule defers entries via the deferral queue when it is not ready to push an entry to the parent schedule, and sets the readiness time corresponding to the entry. Upon the expiration of the readiness time, the child schedule redetermines whether to push the deferred entry corresponding to the deferral queue or optionally to push an interim entry having since arrived. Accordingly, a child schedule receiving a pop requests retains the ability to push an entry at an earlier or later readiness time, and further retains the ability to reconsider which entry to push.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.

Abstract: A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.

Abstract: This invention provides rate shaping in per-flow output queued routing mechanisms for unspecified bit rate service.

Abstract: Rate shaping is provided in per-flow output queued routing mechanisms having output links servicing multiple physical layers.

Abstract: Rate shaping is provided in per-flow queued routing mechanisms for statistical bit rate service.

Abstract: Multiple rate sensitive priority queues reduce relative data transport unit delay variations in time multiplexed from output queued routing mechanisms.

Abstract: Rate shaping is provided in per-flow queued routing mechanisms for available bit rate service. A traffic shaper in a packet switched communications system serially emits packets of time multiplexed flows in substantial compliance with individual network traffic contracts for the respective flows. The individual network traffic contracts include contracts which specify respective peak packet emission rates and associated peak rate tolerances for certain of the flows and which cause each of the flows to fall into mutually exclusive categories. The traffic shaper includes a queuing mechanism and a scheduling mechanism. The queuing mechanism organizes pending packets of active flows, including the certain flows, in respective queues in accordance with an oldest pending packet at head of queue order. The scheduling mechanism is coupled to the queuing mechanism for scheduling the packets of the active flows for emission.