Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Abstract: A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Abstract: A system for integrating multiple electrical system testing functions into a single peripheral component interconnect (PCI) card. The functions of system bring-up and debug are integrated into a single PCI card, which utilizes an operating system and a set of industry standard interfaces to interconnect with standard lab instrumentation. The integrated PCI card utilizes an embedded high performance microprocessor and a compact operating system to provide control over: system-under-test (SUT) power on/off; system device sequencing via programmable General Purpose Input/Output (GPIO); system parametric control (e.g. voltage, temperature, and frequency); system parametric measurement; system debug; and remote control operation via internet interface. In one embodiment, the integrated PCI card comprises the instrumentation controller, Joint Test Action Group (JTAG) Debugger, SUT system controller, and a computer-controlled GPIO card in a single, self aware, half-slot PCI card.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.