Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

Abstract: An apparatus to facilitate a computer system platform boot is disclosed. The apparatus comprises a system on chip (SOC), including a cache memory, a storage device to store platform firmware including boot code, a security controller to load the boot code into the cache during a platform reset and a processor to execute the boot code from the cache memory to initiate the SOC.

Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

Abstract: A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.

Abstract: A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.

Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

Abstract: Techniques for determining a communication interface of a computer platform. In an embodiment, a power management unit of a computer platform provides to an agent of the platform an indication of a power state. In certain embodiments, the agent determines, based on the indication of the power state, that an interface is expected to be available. The agent may designate information for transmission via the first interface—e.g. in lieu of transmitting the information via a second interface which is available prior to the first interface becoming available.

Abstract: Techniques for determining a communication interface of a computer platform. In an embodiment, a power management unit of a computer platform provides to an agent of the platform an indication of a power state. In certain embodiments, the agent determines, based on the indication of the power state, that an interface is expected to be available. The agent may designate information for transmission via the first interface—e.g. in lieu of transmitting the information via a second interface which is available prior to the first interface becoming available.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.