Abstract: Circuits and techniques are described that relate to an “energy operating system” for tracking available energy and energy consumption in a system or device to support a wide range of power management and related functionalities.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.