Abstract: Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.

Abstract: The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

Abstract: Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

Abstract: A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.

Abstract: A system for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which in conjunction with the device proxy agent, assigns the memory space assigned to the device proxy agent to hidden devices. A section of memory is allocated as memory address space for the computer bus. A first portion of the allocated memory address space is assigned to non-hidden computing devices and a second portion of the allocated memory address space is assigned to the device proxy agent. The IOP in conjunction with the device proxy agent assigns the memory address space assigned to the device proxy agent to the hidden devices.

Abstract: A computer system with an Intelligent Input/Output architecture having a plug-and-play control mechanism for assigning and controlling one or more adapters. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices or adapters operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. Initially, a selected adapter is defaulted to an “assigned” state without changing the interrupt routing associated with the adapter. Upon detecting the presence of a driver module that is executable on the IOP, the assigned adapter is marked as “controlled” and the interrupt routing is configured to deliver interrupts to the IOP. Subsequently, the controlled adapter is rendered “hidden” from the host operating system.