Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

Abstract: An apparatus and method is provided for single transfer insert placement. The apparatus receives continuous web material and cuts a discrete section or pad from the web. The pad is then supported on a single transfer surface. The single transfer surface then may spin the supported pad to a desired angle and provide the pad to a receiving surface at a desired interval. The web material can be cut to different insert lengths and the placement location varied.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems.

Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

Abstract: The present invention provides machinery used to create products (for instance disposable products). The machinery is operated at high speed, with the machine occupying a small footprint. Materials can be fed into the manufacturing process vertically (from above or below), using assembly stations to feed completed components into the system at appropriate stations. Additionally, restocking of raw components can be accomplished by robotic means of transferring the raw material from staging areas into infeeding or splicing stations, without the need for human operators.

Abstract: A series of elastic break brakes are provided throughout a travel path of elastics in a machine operation. Elastic strands thread through each individual brake mechanism, and if an elastic strand breaks downstream, a natural snap back of the elastic, which ordinarily travels through the system under tension, drives an immediately upstream cam mechanism back, and holds the elastic thread in place at the elastic break brake immediately upstream of the break as to minimize rethreading required downstream of the elastic break brake.

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract: The present invention provides machinery used to create products (for instance disposable products). The machinery is operated at high speed, with the machine occupying a small footprint. Materials can be fed into the manufacturing process vertically (from above or below), using assembly stations to feed completed components into the system at appropriate stations. Additionally, restocking of raw components can be accomplished by robotic means of transferring the raw material from staging areas into infeeding or splicing stations, without the need for human operators.

Abstract: An apparatus and method is provided for single transfer insert placement. The apparatus receives continuous web material and cuts a discrete section or pad from the web. The pad is then supported on a single transfer surface. The single transfer surface then may spin the supported pad to a desired angle and provide the pad to a receiving surface at a desired interval. The web material can be cut to different insert lengths and the placement location varied.

Abstract: The present invention provides machinery used to create products (for instance disposable products). The machinery is operated at high speed, with the machine occupying a small footprint. Materials can be fed into the manufacturing process vertically (from above or below), using assembly stations to feed completed components into the system at appropriate stations. Additionally, restocking of raw components can be accomplished by robotic means of transferring the raw material from staging areas into infeeding or splicing stations, without the need for human operators.

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract: I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Abstract: A test interface mode over general purpose input/output peripheral connectors of a multichip package (MCP) or system in package (SIP) for an integrated device chip having a wide functional interface. The wide functional interface has more signals than there are available external connectors on the SIP package. Logic in the SIP package includes selection logic to select one or more portions of the wide functional interface to test in a given cycle. Logic in the SIP package multiplexes peripheral connectors as a test interface for the device chip, instead of dedicating connectors on the SIP package for a direct access test interface.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.