Patents by Inventor Christopher J. Pettey

Christopher J. Pettey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9106487
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: August 11, 2015
    Assignee: MELLANOX TECHNOLOGIES LTD.
    Inventor: Christopher J. Pettey
  • Patent number: 9015350
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 21, 2015
    Assignee: Mellanox Technologies Ltd.
    Inventor: Christopher J. Pettey
  • Patent number: 8913615
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 16, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventor: Christopher J. Pettey
  • Patent number: 8346884
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup, which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domains to another and other operations.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 1, 2013
    Assignee: Nextio Inc.
    Inventor: Christopher J. Pettey
  • Publication number: 20120250689
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Application
    Filed: May 9, 2012
    Publication date: October 4, 2012
    Applicant: NEXTIO INC.
    Inventor: Christopher J. Pettey
  • Publication number: 20120221705
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 30, 2012
    Applicant: NEXTIO INC.
    Inventor: Christopher J. Pettey
  • Publication number: 20120218905
    Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 30, 2012
    Applicant: NEXTIO INC.
    Inventor: Christopher J. Pettey
  • Patent number: 8102843
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: January 24, 2012
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 8032659
    Abstract: A network interface controller is provided which is shareable by a plurality of operating system domains (OSDs) within their load-store architecture. The controller includes local resources for corresponding to the OSDs, and global resources corresponding to both the OSDs and a network fabric. A method and apparatus is provided for distinguishing between the local and global resources, for purposes of reset and configuration. The controller allows a reset of only those local resources which are associated with the OSD transmitting the reset. Registration logic allows one of the OSDs to register as master, for configuration and reset of global resources.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 4, 2011
    Assignee: NextIO Inc.
    Inventor: Christopher J. Pettey
  • Patent number: 8032684
    Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: October 4, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Stephen Glaser
  • Patent number: 7979592
    Abstract: A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.
    Type: Grant
    Filed: February 9, 2008
    Date of Patent: July 12, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Stephen Glaser, Asif Khan, Jon Nalley, Stephen Rousset, Tom Saeger, Robert Haskell Utley
  • Publication number: 20110131359
    Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.
    Type: Application
    Filed: September 20, 2010
    Publication date: June 2, 2011
    Applicant: EMULEX DESIGN AND MANUFACTURING CORPORATION
    Inventors: Christopher J. Pettey, Stephen Glaser
  • Patent number: 7953074
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports routes transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. One of the plurality of port initialization logic elements is coupled to the second I/O port and remaining ones of the plurality of port initialization logic elements are each coupled to a corresponding one of the first plurality of I/O ports.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: May 31, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7917658
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains.
    Type: Grant
    Filed: May 25, 2008
    Date of Patent: March 29, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7865654
    Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: January 4, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Stephen Glaser
  • Patent number: 7836211
    Abstract: An apparatus and method are provided that enable I/O devices to be shared and/or partitioned among a plurality of operating system domains within the load-store fabric of each of the operating system domains without requiring modification to the operating system or driver software of the operating system domains. The apparatus includes sharing logic and a first shared input/output (I/O) endpoint. The sharing logic is coupled to a plurality of operating system domains through a load-store fabric. The sharing logic routes transactions between the plurality of operating system domains. The first shared input/output (I/O) endpoint is coupled to the sharing logic. The first shared I/O endpoint requests/completes the transactions for the each of said plurality of operating system domains according to a variant of a protocol that encapsulates an OS domain header within a transaction layer packet.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: November 16, 2010
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7782893
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: August 24, 2010
    Assignee: NextIO Inc.
    Inventors: Christopher J Pettey, Asif Khan, Annette Pagan, Richard E Pekkala, Robert H Utley
  • Patent number: 7706372
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: April 27, 2010
    Assignee: NextIO Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7698483
    Abstract: An apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: April 13, 2010
    Assignee: NextIO, Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7664909
    Abstract: An apparatus and method is provided for allowing one or more processing complexes to share a disk controller, particularly a serial ATA (SATA) controller. Each processing complex utilizes its own load-store domain to couple to the shared SATA controller, either directly, or indirectly through a shared I/O switch. Ultimately, requests from the processing complexes are presented to the switch with operating system domain header (OSD header) information so that the shared SATA controller can determine which request came from which processing complex, and allocate resources accordingly. Upstream responses from the shared SATA controller include the OSD header so that the shared I/O switch can accurately route the responses to their respective processing complexes.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: February 16, 2010
    Assignee: Nextio, Inc.
    Inventor: Christopher J. Pettey