Abstract: A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls an activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor; and activating a low level language microcode program or hardware logic circuit for performing the called activity if the sensing step detects the second type depictor.

Abstract: A method of synchronizing the sequence by which a variety of unrelated activities are executed in a digital processor when the activities are randomly called by multiple callers includes the steps of: providing a single processor queue for holding respective pointers to each different kind of activity that the processor performs; entering the pointer of an activity in the processor queue the first time that the activity is called; providing respective activity queues for each different kind of activity that the processor performs; entering a pointer to the caller of an activity in the respective queue for the called activity each time the activity is called subsequent to its first call; repeatedly executing a single activity pointed to by one pointer in the processor queue until that activity is executed once for each of its callers, provided that if the single activity calls another activity then, executing the single activity only up to the point where the call occurs; and proceeding in the same fashion wit

Abstract: A method of performing a sequence of related activities in multiple digital processors includes the steps of: executing a portion of a first activity of the sequence in a first processor and then executing an INTERPROCESSOR CALL instruction to a second activity in a second processor; suspending execution of the first activity in response to the CALL and signaling the second processor that the second activity has been called by the first activity; completely executing the second activity in the second processor and then executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to the NEXT instruction that the third activity has been called not by the second activity but by the caller of the second activity; and completely executing the third activity in the third processor and, upon completion thereof, signaling the third activity's caller to resume execution of the suspended activity.

Abstract: A method of transmitting isochronous and nonisochronous data through a computer network in which a plurality of stations have respective input and output ports that are serially coupled together to form a loop includes the steps of: transmitting data characters of a nonisochronous frame from a first station in the loop; passing the data characters from the first station through a second station in the loop but with a pair of control characters inserted between any two data characters indicating the beginning and end of an isochronous frame within the nonisochronous frame; passing the data characters and control characters from the second station through a third station on the loop but with another internally generated isochronous data character inserted between the control characters; temporarily stopping the transmitting step in the first station in response to the receipt of at least one of the control characters to pass the isochronous frame through the first station; and proceeding in the first station wi

Abstract: In a parallel data processing system architecture capable of processing in parallel a plurality of data elements from a linear vector stored in a memory module array having in number a power-of-two memory modules, a high degree of conflict-free access to the stored linear vector data elements is achieved through skewed storage wherein a skewing occurs at every Mth address and a further skewing at every M.sup.2 address wherein M (a power-of-two) is equal to the number of memory modules. The data elements are fetched through a connection network for processing in a processor array having in number a power-of-two processors.