Abstract: A capacitor has a known capacitance value for filtering the ripple current of the DC voltage bus. A first modulation index estimator is configured to estimate a first modulation index of the first inverter. A second modulation index estimator configured to estimate a second modulation index of the second inverter. A current estimator is configured to estimate an interleaving phase shift angle associated with a respective one of a set of inverters based on the known capacitance value of the capacitor, the estimated first modulation index, the estimated second modulation index, the first control input and the second control input.

Abstract: An electric machine is coupled to at least the respective alternating current output terminal or to a plurality of alternating current output terminals of the inverter. The electric machine has a rotor with a rotational speed that is capable of converting rotational mechanical energy of the rotor into electrical energy at the direct current bus terminals until the rotational speed declines below a critical speed. In response to the detection of an impaired state of the battery, a controller is configured to provide control signals to switch or toggle the corresponding low-side switch or switches to manage the charging and discharging of the direct current (DC) bus voltage between a minimum DC voltage and a maximum DC voltage that define a range suitable for providing energy sufficient to power an electronic data processor and control logic of the controller.

Abstract: An inverter system is configured to mitigate oscillation of a rotary system that drives a generator or electric machine. A torque damping module is configured to receive a commanded torque or an observed torque and to generate a commanded compensating torque to dampen any mechanical oscillation or resonance of the rotary system based on the observed rotational speed of the generator. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

Abstract: A capacitor has a known capacitance value for filtering the ripple current of the DC voltage bus. A first modulation index estimator is configured to estimate a first modulation index of the first inverter. A second modulation index estimator configured to estimate a second modulation index of the second inverter. A current estimator is configured to estimate an interleaving phase shift angle associated with a respective one of a set of inverters based on the known capacitance value of the capacitor, the estimated first modulation index, the estimated second modulation index, the first control input and the second control input.

Abstract: An inverter system for mitigating oscillation of an electric motor that drives a load comprises a torque command generation module for receiving a commanded torque from an operator of a vehicle. A torque damping module is configured to receive the commanded torque and generating a commanded compensating torque to dampen any mechanical oscillation or resonance of the electric motor based on the observed rotational speed of the motor. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

Abstract: An electric machine is coupled to at least the respective alternating current output terminal or to a plurality of alternating current output terminals of the inverter. The electric machine has a rotor with a rotational speed that is capable of converting rotational mechanical energy of the rotor into electrical energy at the direct current bus terminals until the rotational speed declines below a critical speed. In response to the detection of an impaired state of the battery, a controller is configured to provide control signals to switch or toggle the corresponding low-side switch or switches to manage the charging and discharging of the direct current (DC) bus voltage between a minimum DC voltage and a maximum DC voltage that define a range suitable for providing energy sufficient to power an electronic data processor and control logic of the controller.

Abstract: An inverter system for mitigating oscillation of an electric motor that drives a load comprises a torque command generation module for receiving a commanded torque from an operator of a vehicle. A torque damping module is configured to receive the commanded torque and generating a commanded compensating torque to dampen any mechanical oscillation or resonance of the electric motor based on the observed rotational speed of the motor. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

Abstract: An inverter system is configured to mitigate oscillation of a rotary system that drives a generator or electric machine. A torque damping module is configured to receive a commanded torque or an observed torque and to generate a commanded compensating torque to dampen any mechanical oscillation or resonance of the rotary system based on the observed rotational speed of the generator. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

Abstract: A system and method for controlling an alternating current (AC) motor using a Field Programmable Gate Array (FPGA) to read the current and position measurements in an the AC motor, perform digital filtering of the position and current data, provide very precise synchronization of the measured phase current and position data, and output the data to a phase converter for control of the AC motor.

Abstract: An apparatus for on-demand power management including an I/O serial communication master device, peripheral devices that communicate with the master device along the serial communications bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to reduce energy consumption and system latency.

Abstract: An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.

Abstract: A system and method for controlling an alternating current (AC) motor using a Field Programmable Gate Array (FPGA) to read the current and position measurements in an the AC motor, perform digital filtering of the position and current data, provide very precise synchronization of the measured phase current and position data, and output the data to a phase converter for control of the AC motor.

Abstract: An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.

Abstract: A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.

Abstract: Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is placed on the platform for an identical element of at least two macros. All other elements of the macros are placed at locations on the platform relative to the common element as to satisfy macro placement rules for each macro. Identical elements can be identified by identifying similar elements in a plurality of macros, and creating a common element generic to the similar elements. The user designs a metalization layer to select macros and configure common elements to the selected macros.

Abstract: A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an

Abstract: A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an