Patents by Inventor Christopher J. Waskiewicz

Christopher J. Waskiewicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12356711
    Abstract: VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: July 8, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Christopher J Waskiewicz, Jay William Strane, Hemanth Jagannathan, Brent Anderson
  • Patent number: 12249643
    Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 11, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
  • Patent number: 12243770
    Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 4, 2025
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Yann Mignot, Daniel J. Vincent, Su Chen Fan, Christopher J. Waskiewicz, Hsueh-Chung Chen
  • Patent number: 12136656
    Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: November 5, 2024
    Assignee: International Business Machines Corporation
    Inventors: Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz, Kangguo Cheng
  • Publication number: 20240321630
    Abstract: A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Inventors: Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang, Huai Huang, Koichi Motoyama, Julien Frougier
  • Publication number: 20240203904
    Abstract: A semiconductor structure is provided that includes a stress modulating pattern containing bonding dielectric layer. The stress modulating pattern containing bonding dielectric layer can be formed on a wafer, on a device-containing region that is present on a device wafer, or both a wafer and a device-containing region that is present on a device wafer. The stress modulating pattern is composed of a plurality of patterned structures (metal and/or dielectric) that are embedded at least partially within a bonding dielectric layer. Warpage modulation can be achieved using such a stress modulating pattern containing bonding dielectric layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Inventors: FEE LI LIE, Hosadurga Shobha, Michael Rizzolo, Aakrati Jain, Sagarika Mukesh, Christopher J. Waskiewicz
  • Patent number: 12009422
    Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: June 11, 2024
    Assignee: International Business Machines Corporation
    Inventors: ChoongHyun Lee, Christopher J. Waskiewicz, Chanro Park, Alexander Reznicek
  • Publication number: 20240186391
    Abstract: A semiconductor structure includes a first gate-all-around device disposed on a first region of a substrate and a second gate-all-around device disposed on a second region of the substrate. The first gate-all-around device includes a first metal gate stack surrounding a first channel layer. The first metal gate stack is separated from a first source/drain region by a dielectric inner spacer disposed on opposite sides of the first metal gate stack. The second gate-all-around device includes a second metal gate stack surrounding a second channel layer. The second metal gate stack is separated from a second source/drain region by an epitaxial layer disposed on opposite sides of the second metal gate stack.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Julien Frougier, Sung Dae Suk, Ruilong Xie, Christopher J. Waskiewicz, Veeraraghavan S. Basker
  • Patent number: 11916013
    Abstract: Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Christopher J. Waskiewicz, Eric Miller, Chanro Park
  • Patent number: 11908923
    Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Waskiewicz, Su Chen Fan, Hari Prasad Amanapu, Hemanth Jagannathan
  • Patent number: 11901440
    Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 13, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Christopher J. Waskiewicz, Su Chen Fan, Brent Anderson, Junli Wang
  • Patent number: 11876023
    Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Christopher J. Penny, James John Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry
  • Patent number: 11876124
    Abstract: Embodiments of the invention are directed to a semiconductor device that includes a channel fin; a trench adjacent to an upper region of the channel fin; and an oxygen-blocking layer within the trench. The oxygen-blocking layer includes an oxygen gettering material configured to remove oxygen from an environment to which the oxygen-blocking layer is exposed.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Christopher J. Waskiewicz, Shahab Siddiqui, Ruilong Xie
  • Patent number: 11742350
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: August 29, 2023
    Assignee: International Business Machines Corporation
    Inventors: Andrew Gaul, Chanro Park, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
  • Patent number: 11742246
    Abstract: A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 29, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Hemanth Jagannathan, Christopher J. Waskiewicz, Alexander Reznicek
  • Patent number: 11742354
    Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-? metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: August 29, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Christopher J Waskiewicz, Alexander Reznicek, Su Chen Fan, Heng Wu
  • Publication number: 20230197531
    Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Marc A. Bergendahl, Christopher J. Penny, James John Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry
  • Publication number: 20230187442
    Abstract: A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 15, 2023
    Inventors: Su Chen Fan, Christopher J. Waskiewicz, Yann Mignot, Jeffrey C. Shearer, Hemanth Jagannathan
  • Publication number: 20230144407
    Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 11, 2023
    Inventors: ChoongHyun Lee, Christopher J. Waskiewicz, CHANRO PARK, Alexander Reznicek
  • Patent number: 11646373
    Abstract: A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Waskiewicz, Ruilong Xie, Jay William Strane, Hemanth Jagannathan