Abstract: An apparatus comprising an input to receive identifier parameters for one or more identifiers, where the identifiers are displayable at a display device mounted or mountable in a vehicle. The apparatus may comprise a storage device to store identifier parameters for at least one of the one or more identifiers. The apparatus may also comprise a locating module to determine a location parameter relating to the display device. Also the apparatus may comprise a processor to select an identifier for display at the display device based, at least in part, on the stored identifier parameters for one of the one or more identifiers matching the location parameter relating to the display device.

Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.

Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

Abstract: A data processing system includes processing circuitry for executing context-data-dependent-program instructions which are decoded by decoder circuitry. Such context-data-dependent program instructions perform processing which are dependent upon currently existing context data. As an example, the context-data-dependent program instructions may be floating point instructions and the context data may be rounding mode information. The decoder circuitry supports a context save instruction which saves context data when it is marked as having been used and saves default context data when the current context data is marked as not having been used. The decoder circuitry further supports a context restore instruction which restores context data when the current context data is marked as having been used and permits the current context data to continue for future use when it is marked as currently unused.

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation.

Abstract: A hydraulic implement (1) for portable use includes a hydraulic pump (2), a pump housing (10), a hydraulic cylinder (3) with a piston rod (11), a hydraulic tank (4), hydraulic lines, a compensating device, a manually operable hydraulic control valve (8), a rechargeable battery (9) which is accommodated on the implement (1), and two tool halves (16, 17) that are connected to the piston rod (11) via pivoting arms (12, 13). Each tool half (16, 17) has a wall section (20, 21) that extends perpendicularly to the extension of the longitudinal axis of the piston rod (11). When the tool halves are closed, both wall sections (20, 21) together form a flattened end region (24) that runs perpendicularly to the extension of the longitudinal axis of the piston rod (11).

Abstract: An apparatus comprising an input to receive identifier parameters for one or more identifiers, where the identifiers are displayable at a display device mounted or mountable in a vehicle. The apparatus may comprise a storage device to store identifier parameters for at least one of the one or more identifiers. The apparatus may also comprise a locating module to determine a location parameter relating to the display device. Also the apparatus may comprise a processor to select an identifier for display at the display device based, at least in part, on the stored identifier parameters for one of the one or more identifiers matching the location parameter relating to the display device.

Abstract: An apparatus and method are provided for performing vector processing operations. In particular the apparatus has processing circuitry to perform the vector processing operations and an instruction decoder to decode vector instructions to control the processing circuitry to perform the vector processing operations specified by the vector instructions. The instruction decoder is responsive to a vector generating instruction identifying a scalar start value and wrapping control information, to control the processing circuitry to generate a vector comprising a plurality of elements. In particular, the processing circuitry is arranged to generate the vector such that the first element in the plurality is dependent on the scalar start value, and the values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information.

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence.

Abstract: A high efficiency compact boiler is disclosed which includes a burner configured to introduce combustion gases into an interior region of the boiler, a heat exchange tube made of a length of finned tubing in the form of a helical coil positioned within the interior region of the boiler such that combustion gases from the burner can flow from a region inside the helical coil to a region outside the helical coil, and a floating baffle configured to redirect the flow of combustion gases around the finned tubing as it passes from the region inside the helical coil to the region outside the helical coil, the baffle being positioned proximal adjacent turns of the helical coil and having a coiled configuration corresponding substantially to the helical coil.

Abstract: Methods for classifying subjects and analyzing the relation between subject classification and multiple features of the subjects are provided. Some embodiments of the disclosure provide processes that use clustering analysis as an unsupervised machine learning technique to classify subjects based on multiple features. Some embodiments may associate features of the subjects with a categorical variable on which subject groups are based. This association between the features and the categorical variable of interest (or subject groups) can be obtained by finding featured-based clusters that have similar members as the subject groups. Systems and computer program products implementing the methods are also disclosed.

Abstract: An apparatus comprises processing circuitry, a number of vector register and a number of scalar registers. An instruction decoder is provided which supports decoding of a vector multiply-add instruction specifying at least one vector register and at least one scalar register. In response to the vector multiply-add instruction, the decoder controls the processing circuitry to perform a vector multiply-add instruction in which each lane of processing generates a respective result data element corresponding to a sum of difference of a product value and an addend value, with the product value comprising the product of a respective data element of a first vector value and a multiplier value. In each lane of processing at least one of the multiplier value and the addend value is specified as a portion of a scalar value stored in a scalar register.

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present.

Abstract: An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is 5 responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. Processing circuitry is then used to perform a vector memory access operation in order to access in memory a plurality of data values at addresses determined from an address vector operand 10 comprising a plurality of address elements. The address vector operand is provided in a specified vector register of the vector register set, such that the plurality of elements of the vector stored in that specified vector register form the plurality of address elements.

Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.

Abstract: An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.

Abstract: An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation.

Abstract: An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. Processing circuitry is then used to perform a vector memory access operation in order to access in memory a plurality of data values at addresses determined from an address vector operand comprising a plurality of address elements. The address vector operand is provided in a specified vector register of the vector register set, such that the plurality of elements of the vector stored in that specified vector register form the plurality of address elements.

Abstract: A method and system for provides a user with an ability to capture a sample of an experiential environment and deliver that sample to an interactive service to trigger one or more predetermined events. In exemplary embodiments of the invention such triggered events include the delivery of information and services to the user, the execution of tasks and instructions by the service on the user's behalf, communication events; surveillance events and other control-oriented events that are responsive to the user's wishes. In other exemplary embodiments of the invention, the triggered events include transaction-oriented events, entertainment events, and events associated with enhancements to human ability or function.